Z8F2480AN020SG Zilog, Z8F2480AN020SG Datasheet - Page 200

• Manufacturer Part Number: Z8F2480AN020SG
• Description: MCU 8BIT 24KB FLASH 44LQFP
• Manufacturer: Zilog
• Series: Encore!® XP®r

Specifications of Z8F2480AN020SG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LED, LVD, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 37
• Program Memory Size: 24KB (24K x 8)
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 44-LQFP
• Processor Series: Z8F248x
• Core: eZ8
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 37
• Number Of Timers: 3
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 8 Channel
• For Use With: 770-1002 - ISP 4PORT ZILOG Z8 ENCORE! MCU269-4643 - KIT DEV Z8 ENCORE XP 28-PIN269-4630 - DEV KIT FOR Z8 ENCORE 8K/4K269-4629 - KIT DEV Z8 ENCORE XP 28-PIN269-4628 - KIT DEV Z8 ENCORE XP 8-PIN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4676

Table 103. ADC Data High Byte Register (ADCD_H)
BITS
FIELD
RESET
R/W
ADDR
PS025011-1010
Table 104. ADC Data Low Bits Register (ADCD_L)
BITS
FIELD
RESET
R/W
ADDR
Bit Position
[7:0]
Bit Position
[7,6]
[5:0]
Reserved
ADC Data High Byte Register
ADC Data Low Bit Register
7
7
The ADC Data High Byte Register
output. Access to the ADC Data High Byte Register is Read-only. Reading the ADC Data
High Byte Register latches data in the ADC Low Bits Register.
Value (H)
00–FF
The ADC Data Low Bit Register
well as an overflow status bit. Access to the ADC Data Low Bits Register is Read-Only.
Reading the ADC Data High Byte Register latches data in the ADC Low Bits Register.
Value (H)
00–11b
0
ADCDL
R
X
6
6
Description
ADC High Byte
The last conversion output is held in the data registers until the 
next ADC conversion has completed.
Description
ADC Low Bit
These bits are the 2 least significant bits of the 10-bit ADC output. 
These bits are undefined after a Reset. The low bits are latched into 
this register whenever the ADC Data High Byte register is read.
Reserved—Must be 0.
5
5
P R E L I M I N A R Y
(Table 104)
4
4
(Table
ADCDH
F73H
F72H
R
X
103) contains the upper eight bits of the ADC
contains the lower bits of the ADC output as
3
3
Reserved
R
X
Z8 Encore! XP
2
2
Product Specification
Analog-to-Digital Converter
1
1
®
F1680 Series
0
0
186