Z8F2480AN020SG Zilog, Z8F2480AN020SG Datasheet - Page 225

• Manufacturer Part Number: Z8F2480AN020SG
• Description: MCU 8BIT 24KB FLASH 44LQFP
• Manufacturer: Zilog
• Series: Encore!® XP®r

Specifications of Z8F2480AN020SG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LED, LVD, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 37
• Program Memory Size: 24KB (24K x 8)
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 44-LQFP
• Processor Series: Z8F248x
• Core: eZ8
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 37
• Number Of Timers: 3
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 8 Channel
• For Use With: 770-1002 - ISP 4PORT ZILOG Z8 ENCORE! MCU269-4643 - KIT DEV Z8 ENCORE XP 28-PIN269-4630 - DEV KIT FOR Z8 ENCORE 8K/4K269-4629 - KIT DEV Z8 ENCORE XP 28-PIN269-4628 - KIT DEV Z8 ENCORE XP 8-PIN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4676

Table 115. ESPI State Register (ESPISTATE)
PS025011-1010
BITS
FIELD
RESET
R/W
ADDR
ESPI State Register
SCKI
R
7
0
TUND—Transmit Underrun
0 = A Transmit Underrun error has not occurred.
1 = A Transmit Underrun error has occurred.
COL—Collision
0 = A multi-Master collision (mode fault) has not occurred.
1 = A multi-Master collision (mode fault) has occurred.
ABT—Slave mode transaction abort
This bit is set if the ESPI is configured in SLAVE mode, a transaction is occurring and SS
deasserts before all bits of a character have been transferred as defined by the NUMBITS
field of the ESPIMODE register. This bit can also be set in SLAVE mode by an SCK
monitor timeout (MMEN = 0, BRGCTL = 1).
0 = A SLAVE mode transaction abort has not occurred.
1 = A SLAVE mode transaction abort has occurred.
ROVR—Receive Overrun
0 = A Receive Overrun error has not occurred.
1 = A Receive Overrun error has occurred.
RDRNE—Receive Data Register Not Empty
0 = Receive Data register is empty.
1 = Receive Data register is not empty.
TFST—Transfer Status
0 = No data transfer is currently in progress.
1 = Data transfer is currently in progress.
SLAS—Slave Select
Reading this bit returns the current value of the SS pin.
0 = The SS pin input is Low.
1 = The SS pin input is High.
The ESPI State register
internal state.
SDI
R
6
0
5
(Table
P R E L I M I N A R Y
115) lets you observe the ESPI clock, data and 
4
F65H
3
ESPISTATE
R
0
Z8 Encore! XP
Enhanced Serial Peripheral Interface
2
Product Specification
1
®
F1680 Series
0
211