HD64F2338VFC25 Renesas Electronics America, HD64F2338VFC25 Datasheet
HD64F2338VFC25
Specifications of HD64F2338VFC25
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HD64F2338VFC25 Summary of contents
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To our customers, Old Company Name in Catalogs and Other Documents st On April 1 , 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the ...
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All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm ...
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The revision list can be viewed directly by clicking the title page. The revision list summarizes the locations of revisions and additions. Details should always be checked by referring to the relevant text. H8S/2339 Group 16 Hardware Manual Renesas 16-Bit ...
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This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in ...
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General Precautions in the Handling of MPU/MCU Products The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes on the products covered by this manual, refer to the relevant sections of the manual. If ...
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Rev.4.00 Sep. 07, 2007 Page iv of xxx ...
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This LSI is a single-chip microcomputer made up of the H8S/2000 CPU with an internal 32-bit architecture as its core, and the peripheral functions required to configure a system. This LSI is equipped with ROM, RAM, a bus controller, data ...
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H8S/2339 Group Manuals: Document Title H8S/2339 Group Hardware Manual H8S/2600 Series, H8S/2000 Series Software Manual User’s Manuals for Development Tools: Document Title H8S, H8/300 Series C/C++ Compiler, Assembler, Optimized Linkage Editor Compiler Package Ver.6.01 User’s Manual H8S, H8/300 Series Simulator/Debugger ...
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Main Revisions for This Edition Item Page 1.1 Overview 6 Table 1.1 Overview 1.3.1 Pin 10 Arrangement Figure 1.4 HD64F2339E Pin Arrangement (TFP- 144G: Top View) Revision (See Manual for Details) Table amended Item Specification Product lineup Model HD64F2339E* HD64F2339 ...
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Item Page 6.3.5 Chip Select 153 Signals Section 13 Watchdog 579 to 594 Note shown below deleted Timer 14.2.8 Bit Rate 616 Register (BRR) Table 14.3 BRR Settings for Various Bit Rates (Asynchronous Mode) 19.4.1 Features 738 Rev.4.00 Sep. 07, ...
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Item Page 19.13.1 Features 789 22.2.6 Flash Memory 910 Characteristics Table 22.21 Flash Memory Characteristics 911 D.1 Port States in 1207 Each Mode Table D.1 I/O Port 1208 States in Each Processing State Revision (See Manual for Details) Description amended ...
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All trademarks and registered trademarks are the property of their respective owners. Rev.4.00 Sep. 07, 2007 Page x of xxx ...
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Section 1 Overview ............................................................................................................. 1.1 Overview........................................................................................................................... 1.2 Block Diagram .................................................................................................................. 1.3 Pin Description.................................................................................................................. 1.3.1 Pin Arrangement .................................................................................................. 1.3.2 Pin Functions in Each Operating Mode ............................................................... 11 1.4 Pin Functions .................................................................................................................... 17 Section 2 CPU ...................................................................................................................... 25 2.1 Overview........................................................................................................................... 25 2.1.1 ...
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Bus-Released State............................................................................................... 64 2.8.6 Power-Down State ............................................................................................... 65 2.9 Basic Timing..................................................................................................................... 65 2.9.1 Overview.............................................................................................................. 65 2.9.2 On-Chip Memory (ROM, RAM) ......................................................................... 65 2.9.3 On-Chip Supporting Module Access Timing....................................................... 67 2.9.4 External Address Space Access Timing .............................................................. 68 2.10 Usage ...
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Exception Handling Operation............................................................................. 88 4.1.3 Exception Vector Table ....................................................................................... 88 4.2 Reset ................................................................................................................................. 90 4.2.1 Overview.............................................................................................................. 90 4.2.2 Reset Sequence .................................................................................................... 90 4.2.3 Interrupts after Reset............................................................................................ 91 4.2.4 State of On-Chip Supporting Modules after Reset Release ................................. 91 4.3 ...
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DTC and DMAC Activation by Interrupt ......................................................................... 125 5.6.1 Overview.............................................................................................................. 125 5.6.2 Block Diagram..................................................................................................... 126 5.6.3 Operation ............................................................................................................. 127 Section 6 Bus Controller 6.1 Overview........................................................................................................................... 129 6.1.1 Features................................................................................................................ 129 6.1.2 Block Diagram..................................................................................................... 131 6.1.3 Pin Configuration................................................................................................. 132 6.1.4 Register ...
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Precharge State Control ....................................................................................... 171 6.5.8 Wait Control ........................................................................................................ 172 6.5.9 Byte Access Control ............................................................................................ 174 6.5.10 Burst Operation.................................................................................................... 176 6.5.11 Refresh Control.................................................................................................... 179 6.6 DMAC Single Address Mode and DRAM Interface ........................................................ 183 6.6.1 When DDS = 1..................................................................................................... ...
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DMA Control Register (DMACR)....................................................................... 211 7.2.5 DMA Band Control Register (DMABCR) .......................................................... 215 7.3 Register Descriptions (2) (Full Address Mode) ................................................................ 221 7.3.1 Memory Address Register (MAR)....................................................................... 221 7.3.2 I/O Address Register (IOAR) .............................................................................. 221 7.3.3 Execute Transfer Count ...
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DTC Mode Register A (MRA) ............................................................................ 298 8.2.2 DTC Mode Register B (MRB)............................................................................. 299 8.2.3 DTC Source Address Register (SAR).................................................................. 301 8.2.4 DTC Destination Address Register (DAR).......................................................... 301 8.2.5 DTC Transfer Count Register A (CRA) .............................................................. 302 8.2.6 DTC ...
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Overview.............................................................................................................. 361 9.5.2 Register Configuration......................................................................................... 361 9.5.3 Pin Functions ....................................................................................................... 362 9.6 Port 5................................................................................................................................. 362 9.6.1 Overview.............................................................................................................. 362 9.6.2 Register Configuration......................................................................................... 364 9.6.3 Pin Functions ....................................................................................................... 368 9.7 Port 6................................................................................................................................. 370 9.7.1 Overview.............................................................................................................. 370 9.7.2 Register Configuration......................................................................................... 371 9.7.3 ...
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Register Configuration......................................................................................... 414 9.14.3 Pin Functions ....................................................................................................... 416 9.14.4 MOS Input Pull-Up Function............................................................................... 418 9.15 Port E ................................................................................................................................ 419 9.15.1 Overview.............................................................................................................. 419 9.15.2 Register Configuration......................................................................................... 420 9.15.3 Pin Functions ....................................................................................................... 423 9.15.4 MOS Input Pull-Up Function............................................................................... 425 9.16 Port ...
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Synchronous Operation........................................................................................ 488 10.4.4 Buffer Operation .................................................................................................. 490 10.4.5 Cascaded Operation ............................................................................................. 494 10.4.6 PWM Modes ........................................................................................................ 496 10.4.7 Phase Counting Mode .......................................................................................... 502 10.5 Interrupts ........................................................................................................................... 508 10.5.1 Interrupt Sources and Priorities............................................................................ 508 10.5.2 DTC/DMAC Activation....................................................................................... 510 10.5.3 ...
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Section 12 8-Bit Timers 12.1 Overview........................................................................................................................... 555 12.1.1 Features................................................................................................................ 555 12.1.2 Block Diagram..................................................................................................... 556 12.1.3 Pin Configuration................................................................................................. 557 12.1.4 Register Configuration......................................................................................... 557 12.2 Register Descriptions ........................................................................................................ 558 12.2.1 Timer Counters 0 and 1 (TCNT0, TCNT1) ......................................................... 558 12.2.2 Time Constant ...
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Reset Control/Status Register (RSTCSR)............................................................ 585 13.2.4 Notes on Register Access..................................................................................... 586 13.3 Operation........................................................................................................................... 587 13.3.1 Operation in Watchdog Timer Mode ................................................................... 587 13.3.2 Operation in Interval Timer Mode ....................................................................... 589 13.3.3 Timing of Overflow Flag (OVF) Setting ............................................................. 590 ...
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Section 15 Smart Card Interface 15.1 Overview........................................................................................................................... 665 15.1.1 Features................................................................................................................ 665 15.1.2 Block Diagram..................................................................................................... 666 15.1.3 Pin Configuration................................................................................................. 667 15.1.4 Register Configuration......................................................................................... 668 15.2 Register Descriptions ........................................................................................................ 669 15.2.1 Smart Card Mode Register (SCMR) .................................................................... 669 15.2.2 Serial Status Register ...
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Usage Notes ...................................................................................................................... 716 Section 17 D/A Converter 17.1 Overview........................................................................................................................... 721 17.1.1 Features................................................................................................................ 721 17.1.2 Block Diagram..................................................................................................... 722 17.1.3 Pin Configuration................................................................................................. 723 17.1.4 Register Configuration......................................................................................... 723 17.2 Register Descriptions ........................................................................................................ 724 17.2.1 D/A Data Registers (DADR0 ...
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Register Configuration......................................................................................... 747 19.5 Register Descriptions ........................................................................................................ 748 19.5.1 Flash Memory Control Register 1 (FLMCR1)..................................................... 748 19.5.2 Flash Memory Control Register 2 (FLMCR2)..................................................... 751 19.5.3 Erase Block Register 1 (EBR1) ........................................................................... 752 19.5.4 Erase Block Registers 2 (EBR2).......................................................................... 752 ...
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On-Board Programming Modes........................................................................... 792 19.13.5 Flash Memory Emulation in RAM ...................................................................... 794 19.13.6 Differences between Boot Mode and User Program Mode ................................. 795 19.13.7 Block Configuration............................................................................................. 796 19.13.8 Pin Configuration................................................................................................. 797 19.13.9 Register Configuration......................................................................................... 798 19.14 Register Descriptions ........................................................................................................ ...
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Flash Memory Programming and Erasing Precautions ..................................................... 841 Section 20 Clock Pulse Generator 20.1 Overview........................................................................................................................... 847 20.1.1 Block Diagram..................................................................................................... 847 20.1.2 Register Configuration......................................................................................... 848 20.2 Register Descriptions ........................................................................................................ 848 20.2.1 System Clock Control Register (SCKCR) ........................................................... 848 20.3 Oscillator........................................................................................................................... ...
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Section 22 Electrical Characteristics 22.1 Electrical Characteristics of Mask ROM Version (H8S/2338, H8S/2337) and ROMless Version (H8S/2332) ................................................................................... 871 22.1.1 Absolute Maximum Ratings ................................................................................ 871 22.1.2 DC Characteristics ............................................................................................... 872 22.1.3 AC Characteristics ............................................................................................... 874 22.1.4 A/D Conversion Characteristics........................................................................... 898 ...
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C.10 Port A............................................................................................................................... 1182 C.11 Port B ............................................................................................................................... 1185 C.12 Port C ............................................................................................................................... 1186 C.13 Port D............................................................................................................................... 1187 C.14 Port E ............................................................................................................................... 1188 C.15 Port F................................................................................................................................ 1189 C.16 Port G............................................................................................................................... 1197 Appendix D Pin States ...................................................................................... D.1 Port States in ...
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Overview The H8S/2339 Group is a series of microcomputers (MCUs: microcomputer units), built around the H8S/2000 CPU, employing Renesas’ proprietary architecture, and equipped with peripheral functions on-chip. The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen ...
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Table 1.1 Overview Item Specification • CPU General-register machine ⎯ Sixteen 16-bit general registers (also usable as sixteen 8-bit registers or eight 32-bit registers) • High-speed operation suitable for realtime control ⎯ Maximum clock rate: 25 MHz ⎯ High-speed arithmetic ...
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Item Specification • Data transfer Can be activated by internal interrupt or software controller (DTC) • Multiple transfers or multiple types of transfer possible for one activation source • Transfer possible in repeat mode, block transfer mode, etc. • Request ...
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Item Specification • Memory Flash memory and mask ROM • High-speed static RAM Product Name H8S/2339 H8S/2338 H8S/2337 H8S/2332 Nine external interrupt pins (NMI, IRQ • Interrupt controller • 52 internal interrupt sources • Eight priority levels settable Power-down state ...
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Item Specification • Operating modes Eight MCU operating modes (H8S/2338 F-ZTAT) CPU Operating Mode Mode 1 — Advanced — Advanced 11 12 — Advanced 15 • Four MCU operating ...
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Item Specification • Clock pulse Built-in duty correction circuit generator Product lineup Operating power supply voltage 2.7 to 3.6 V Operating frequency Model HD64F2339E* HD64F2339 HD6432338 HD64F2338 HD6432337 HD6412332 O: Products in the current lineup Note: * The on-chip debug ...
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Block Diagram EXTAL XTAL STBY RES WDTOVF FWE(EMLE NMI PF /φ / / /HWR Port 4 PF /LWR /LCAS/BREQO 2 PF /BACK ...
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Pin Description 1.3.1 Pin Arrangement Figures 1.2 and 1.3 show the pin arrangement of the H8S/2339 Group. P5 /AN 109 /AN 110 /AN /DA 111 /AN /DA 112 7 ...
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P5 /AN 109 /AN 110 /AN /DA 111 /AN /DA 112 113 CC V 114 ref P4 /AN 115 /AN 116 1 1 ...
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P5 /AN 109 /AN 110 /AN /DA 111 /AN /DA 112 113 CC V 114 ref P4 /AN 115 /AN 116 1 1 ...
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Pin Functions in Each Operating Mode Table 1.2 Pin Functions in Each Operating Mode Pin No. Mode FP-144G 1 P8 /DACK /DACK /WAIT 6 5 ...
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Pin No. Mode FP-144G /IRQ /IRQ /IRQ 5 5 ...
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Pin No. Mode FP-144G /TxD /TxD /RxD /RxD ...
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Pin No. Mode FP-144G 86 P2 /PO /TIOCA WDTOVF 87 RES 88 89 NMI STBY XTAL 93 EXTAL /φ FWE ...
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Pin No. Mode FP-144G 113 AV CC 114 V ref 115 P4 / 116 P4 / 117 P4 / 118 P4 / 119 P4 / 120 P4 ...
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Pin No. Mode FP-144G 137 MD 2 138 P8 /TEND 2 0 139 P8 /TEND 3 1 140 PG /CAS 0 141 PG / 142 PG / 143 PG / 144 ...
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Pin Functions Table 1.3 Pin Functions Type Symbol Power Clock XTAL EXTAL φ Pin No. FP-144G I/O Name and Function 3, 39, Input Power supply: For connection to the power 61, 91, supply. All V ...
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Type Symbol Operating mode control MD 0 Rev.4.00 Sep. 07, 2007 Page 18 of 1210 REJ09B0245-0400 Pin No. FP-144G I/O Name and Function 137 to Input Mode pins: These pins set the operating mode. 135 The relation ...
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Type Symbol Operating mode control RES System control STBY BREQ BREQO BACK FWE * 1 EMLE * 2 Pin No. FP-144G I/O Name and Function 137 to 135 Input H8S/2339 F-ZTAT, Mask ROM, and ROMless ...
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Type Symbol Interrupts NMI IRQ to 7 IRQ 0 Address bus Data bus Bus control HWR LWR CAS LCAS Rev.4.00 Sep. 07, 2007 ...
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Type Symbol WAIT Bus control DREQ DMA controller , 1 DREQ (DMAC) 0 TEND , 1 TEND 0 DACK , 1 DACK 0 16-bit timer TCLKD to pulse unit TCLKA (TPU) TIOCA , 0 TIOCB , 0 TIOCC , 0 ...
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Type Symbol Programmable pulse generator PO 0 (PPG) 8-bit timer TMO , 0 TMO 1 TMCI , 0 TMCI 1 TMRI , 0 TMRI 1 WDTOVF Watchdog timer (WDT) Serial TxD , 2 communication TxD , 1 ...
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Type Symbol A/D converter AV CC and D/A converter ref I/O ports ...
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Type Symbol I/O ports ...
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Overview The H8S/2000 CPU is a high-speed central processing unit with an internal 32-bit architecture that is upward-compatible with the H8/300 and H8/300H CPUs. The H8S/2000 CPU has sixteen 16-bit general registers, can address a 16-Mbyte (architecturally 4-Gbyte) linear ...
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High-speed operation ⎯ All frequently-used instructions execute in one or two states ⎯ Maximum clock rate: ⎯ 8/16/32-bit register-register add/subtract ⎯ 8 × 8-bit register-register multiply: ⎯ 16 ÷ 8-bit register-register divide: ⎯ 16 × 16-bit register-register ...
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Differences from H8/300 CPU In comparison to the H8/300 CPU, the H8S/2000 CPU has the following enhancements. • More general registers and control registers ⎯ Eight 16-bit expanded registers, and one 8-bit control register, have been added. • Expanded ...
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CPU Operating Modes The H8S/2339 Group CPU has advanced operating mode. Advanced mode supports a maximum 16-Mbyte total address space (architecturally a maximum 16-Mbyte program area and a maximum of 4 Gbytes for program and data areas combined). The ...
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Exception Vector Table and Memory Indirect Branch Addresses: In advanced mode the top area starting at H'00000000 is allocated to the exception vector table in units of 32 bits. In each 32 bits, the upper 8 bits are ignored and ...
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Stack Structure: In advanced mode, when the program counter (PC) is pushed onto the stack in a subroutine call, and the PC, condition-code register (CCR), and extended control register (EXR) are pushed onto the stack in exception handling, they are ...
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Address Space Figure 2.3 shows a memory map of the H8S/2000 CPU. The H8S/2000 CPU provides linear access to a maximum 16-Mbyte (architecturally 4-Gbyte) address space in advanced mode. H'00000000 H'00FFFFFF H'FFFFFFFF Program area Cannot be used by the ...
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Register Configuration 2.4.1 Overview The CPU has the internal registers shown in figure 2.4. There are two types of registers: general registers and control registers. General Registers (Rn) and Extended Registers (En) 15 ER0 ER1 ER2 ER3 ER4 ER5 ...
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General Registers The CPU has eight 32-bit general registers. These general registers are all functionally alike and can be used as both address registers and data registers. When a general register is used as a data register, it can ...
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SP (ER7) 2.4.3 Control Registers The control registers are the 24-bit program counter (PC), 8-bit extended control register (EXR), and 8-bit condition-code register (CCR). (1) Program Counter (PC) This 24-bit counter indicates the address of the next instruction the CPU ...
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Condition-Code Register (CCR) This 8-bit register contains internal CPU status information, including an interrupt mask bit (I) and half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags. Bit 7—Interrupt Mask Bit (I): Masks interrupts other than ...
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Operations can be performed on the CCR bits by the LDC, STC, ANDC, ORC, and XORC instructions. The and C flags are used as branching conditions for conditional branch (Bcc) instructions. 2.4.4 Initial Register Values Reset exception ...
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General Register Data Formats Figure 2.7 shows the data formats in general registers. Data Type Register Number 1-bit data RnH 1-bit data RnL 4-bit BCD data RnH 4-bit BCD data RnL Byte data RnH Byte data RnL Figure 2.7 ...
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Data Type Register Number Word data Rn Word data En 15 MSB Longword data ERn 31 MSB En Legend: ERn: General register ER En: General register E Rn: General register R RnH: General register RH RnL: General register RL MSB: ...
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Memory Data Formats Figure 2.8 shows the data formats in memory. The CPU can access word data and longword data in memory, but word or longword data must begin at an even address attempt is made to ...
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Instruction Set 2.6.1 Overview The H8S/2000 CPU has 65 types of instructions. The instructions are classified by function in table 2.1. Table 2.1 Instruction Classification Function Instructions Data transfer MOV POP * 1 , PUSH * LDM, STM MOVFPE, ...
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Instructions and Addressing Modes Table 2.2 indicates the combinations of instructions and addressing modes that the H8S/2600 CPU can use. Table 2.2 Combinations of Instructions and Addressing Modes Function Instruction MOV BWL BWL Data transfer POP, PUSH — — ...
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Table of Instructions Classified by Function Table 2.3 summarizes the instructions in each functional category. The notation used in table 2.3 is defined below. Operation Notation General register (destination General register (source General register * ...
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Table 2.3 Instructions Classified by Function Type Instruction Data transfer MOV MOVFPE MOVTPE POP PUSH LDM STM Size * 1 Function (EAs) → Rd, Rs → (Ead) B/W/L Moves data between two general registers or between a general register and ...
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Type Instruction Arithmetic ADD operations SUB ADDX SUBX INC DEC ADDS SUBS DAA DAS MULXU MULXS DIVXU Rev.4.00 Sep. 07, 2007 Page 44 of 1210 REJ09B0245-0400 Size * 1 Function Rd ± Rs → Rd, Rd ± #IMM → Rd ...
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Type Instruction Arithmetic DIVXS operations CMP NEG EXTU EXTS TAS Size * 1 Function Rd ÷ Rs → Rd B/W Performs signed division on data in two general registers: either 16 bits ÷ 8 bits → 8-bit quotient and 8-bit ...
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Type Instruction Logic AND operations OR XOR NOT Shift SHAL operations SHAR SHLL SHLR ROTL ROTR ROTXL ROTXR Rev.4.00 Sep. 07, 2007 Page 46 of 1210 REJ09B0245-0400 Size * 1 Function Rd ∧ Rs → Rd, Rd ∧ #IMM → ...
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Type Instruction Bit- BSET manipulation instructions BCLR BNOT BTST BAND BIAND BOR BIOR Size * 1 Function 1 → (<bit-No.> of <EAd>) B Sets a specified bit in a general register or memory operand to 1. The bit number is ...
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Type Instruction Bit- BXOR manipulation instructions BIXOR BLD BILD BST BIST Rev.4.00 Sep. 07, 2007 Page 48 of 1210 REJ09B0245-0400 Size * 1 Function C ⊕ (<bit-No.> of <EAd>) → Exclusive-ORs the carry flag with a specified bit ...
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Type Instruction Branch Bcc instructions JMP BSR JSR RTS Size * 1 Function — Branches to a specified address if a specified condition is true. The branching conditions are listed below. Mnemonic BRA(BT) BRN(BF) BHI BLS BCC(BHS) BCS(BLO) BNE BEQ ...
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Type Instruction System control TRAPA instructions RTE SLEEP LDC STC ANDC ORC XORC NOP Rev.4.00 Sep. 07, 2007 Page 50 of 1210 REJ09B0245-0400 Size * 1 Function — Starts trap-instruction exception handling. — Returns from an exception-handling routine. — Causes ...
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Type Instruction Block data EEPMOV.B transfer instruction EEPMOV.W Notes: 1. Size refers to the operand size. B: Byte W: Word L: Longword 2. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction. Size * ...
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Basic Instruction Formats The CPU instructions consist of 2-byte (1-word) units. An instruction consists of an operation field (op field), a register field (r field), an effective address extension (EA field), and a condition field (cc). Figure 2.9 shows ...
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Addressing Modes and Effective Address Calculation 2.7.1 Addressing Mode The CPU supports the eight addressing modes listed in table 2.4. Each instruction uses a subset of these addressing modes. Arithmetic and logic instructions can use the register direct and ...
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Register Indirect with Post-Increment or Pre-Decrement—@ERn+ or @-ERn: • Register indirect with post-increment—@ERn+ The register field of the instruction code specifies an address register (ERn) which contains the address of a memory operand. After the operand is accessed, 1, ...
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Immediate—#xx:8, #xx:16, or #xx:32: The instruction contains 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) immediate data as an operand. The ADDS, SUBS, INC, and DEC instructions contain immediate data implicitly. Some bit manipulation instructions contain 3-bit immediate data in ...
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If an odd address is specified in word or longword memory access branch address, the least significant bit is regarded as 0, causing data to be accessed or instruction code to be fetched at the address preceding ...
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Table 2.6 Effective Address Calculation Rev.4.00 Sep. 07, 2007 Page 57 of 1210 REJ09B0245-0400 ...
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Processing States 2.8.1 Overview The CPU has five main processing states: the reset state, exception handling state, program execution state, bus-released state, and power-down state. Figure 2.11 shows a diagram of the processing states. Figure 2.12 indicates the state ...
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End of bus request Bus-released state End of exception handling Exception-handling state RES = high *1 Reset state Notes: 1. From any state except hardware standby mode, a transition to the reset state occurs whenever RES goes low. A transition ...
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Exception-Handling State The exception-handling state is a transient state that occurs when the CPU alters the normal processing flow due to a reset, interrupt, or trap instruction. The CPU fetches a start address (vector) from the exception vector table ...
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Reset Exception Handling After the RES pin has gone low and the reset state has been entered, when RES goes high again, reset exception handling starts. When reset exception handling starts the CPU fetches a start address (vector) from ...
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Advanced mode SP CCR PC (24 bits) (c) Interrupt control mode 0 Note: * Ignored when returning. Figure 2.13 Stack Structure after Exception Handling (Examples) 2.8.4 Program Execution State In this state the CPU executes program instructions in sequence. 2.8.5 ...
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Power-Down State The power-down state includes both modes in which the CPU stops operating and modes in which the CPU does not stop. There are three modes in which the CPU stops operating: sleep mode, software standby mode, and ...
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Internal address bus Internal read signal Read access Internal data bus Internal write signal Write access Internal data bus Figure 2.14 On-Chip Memory Access Cycle φ Address bus AS RD HWR, LWR Data bus Figure 2.15 Pin States during ...
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On-Chip Supporting Module Access Timing The on-chip supporting modules are accessed in two states. The data bus is either 8 bits or 16 bits wide, depending on the particular internal I/O register being accessed. Figure 2.16 shows the access ...
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Address bus AS RD HWR, LWR Data bus Figure 2.17 Pin States during On-Chip Supporting Module Access 2.9.4 External Address Space Access Timing The external address space is accessed with an 8-bit or 16-bit data bus width in a ...
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Section 3 MCU Operating Modes 3.1 Overview 3.1.1 Operating Mode Selection (H8S/2338 F-ZTAT) This version has eight operating modes (modes 10, 11, 14, and 15). These modes are determined by the mode pin (MD operating mode and ...
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The CPU's architecture allows for 4 Gbytes of address space, but this version actually accesses a maximum of 16 Mbytes. Modes are externally expanded modes that allow access to external memory and peripheral devices. The external expansion ...
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Table 3.2 MCU Operating Mode Selection (Mask ROM and ROMless Versions, H8S/2339 F-ZTAT) MCU Operating Mode ...
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Register Configuration The chip has a mode control register (MDCR) that indicates the inputs at the mode pins (MD ), and a system control register (SYSCR) and system control register 2 (SYSCR2 control the operation of ...
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System Control Register (SYSCR) Bit : 7 — Initial value : 0 R/W : R/W Bit 7—Reserved: Only 0 should be written to this bit. Bit 6—Reserved: This bit is always read as 0, and cannot be modified. Bits ...
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Bit 1 IRQPAS Description are used for IRQ are used for IRQ Bit 0—RAM Enable (RAME): Enables or disables the on-chip RAM. The RAME bit is initialized when ...
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Bit 0—Reserved: In the H8S/2338 F-ZTAT, this bit is always read as 0 and should only be written with 0. In the H8S/2339 F-ZTAT, this bit is reserved and should only be written with 0. 3.3 Operating Mode Descriptions 3.3.1 ...
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Mode 6 (Expanded Mode with On-Chip ROM Enabled) The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is enabled. Ports A, B, and C function as input ports immediately after a reset. These pins ...
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Mode 14 (H8S/2338 F-ZTAT Only) This is a flash memory user program mode. For details, see section 19, ROM. Except for the fact that flash memory programming and erasing can be performed, operation in this mode is the same ...
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Pin Functions in Each Operating Mode The pin functions of ports vary depending on the operating mode. Table 3.4 shows their functions in each operating mode. Table 3.4 Pin Functions in Each Mode Mode 2 * ...
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Mode 2 Boot Mode (advanced expanded mode with on-chip ROM enabled) H'000000 On-chip ROM H'010000 On-chip ROM/ external address H'060000 Reseved area H'080000 External address H'FF7400 Reseved area H'FF7C00 On-chip RAM External address H'FFFC00 H'FFFE50 H'FFFF08 External address H'FFFF28 H'FFFFFF ...
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Modes 4 and 5 (advanced expanded modes with on-chip ROM disabled) H'000000 External address space H'060000 *4 Reseved area H'080000 External address space H'FF7400 *4 Reseved area H'FF7C00 *3 On-chip RAM External address H'FFFC00 space H'FFFE50 Internal I/O registers H'FFFF08 ...
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Modes 4 and 5 (advanced expanded modes with on-chip ROM disabled) H'000000 External address space H'FFDC00 *3 On-chip RAM External address H'FFFC00 space H'FFFE50 Internal I/O registers H'FFFF08 External address space H'FFFF28 Internal I/O registers H'FFFFFF Notes: 1. External addresses ...
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Mode 10 Boot Mode (advanced expanded mode with on-chip ROM enabled) H'000000 H'010000 H'040000 External address H'FFDC00 External address H'FFFC00 H'FFFE50 H'FFFF08 External address H'FFFF28 H'FFFFFF Notes: 1. External addresses when EAE = 1 in BCRL; on-chip ROM when EAE ...
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Mode 14 User Program Mode (advanced expanded mode with on-chip ROM enabled) H'000000 On-chip ROM H'010000 On-chip ROM/ external address space H'040000 External address space H'FFDC00 On-chip RAM External address H'FFFC00 H'FFFE50 Internal I/O registers H'FFFF08 External address H'FFFF28 Internal ...
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Modes 4 and 5 (advanced expanded modes with on-chip ROM disabled) H'000000 External address space H'FFDC00 *4 On-chip RAM External address H'FFFC00 space H'FFFE50 Internal I/O registers H'FFFF08 External address space H'FFFF28 Internal I/O registers H'FFFFFF Notes: 1. External addresses ...
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H'000000 H'FFDC00 H'FFFC00 H'FFFE50 H'FFFF08 H'FFFF28 H'FFFFFF Note: * External addresses can be accessed by clearing the RAME bit in SYSCR to 0. Figure 3.4 H8S/2332 Memory Map in Each Operating Mode Modes 4 and 5 (advanced expanded modes with ...
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Section 4 Exception Handling 4.1 Overview 4.1.1 Exception Handling Types and Priority As table 4.1 indicates, exception handling may be caused by a reset, trap instruction, or interrupt. Exception handling is prioritized as shown in table 4.1. If two or ...
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Exception Handling Operation Exceptions originate from various sources. Trap instructions and interrupts are handled as follows: 1. The program counter (PC), condition code register (CCR), and extend register (EXR) are pushed onto the stack. 2. The interrupt mask bits ...
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Table 4.2 Exception Vector Table Exception Source Reset Reserved Reserved for system use Trace Reserved for system use External interrupt NMI Trap instruction (4 sources) Reserved for system use External interrupt IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 Internal ...
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Reset 4.2.1 Overview A reset has the highest exception priority. When the RES pin goes low, all processing halts and the chip enters the reset state. A reset initializes the internal state of the CPU and the registers of ...
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RES Address bus RD HWR, LWR (1), (3) Reset exception handling vector address ((1) = H'000000, (3) = H'000002) (2), (4) Start address (contents of reset exception vector address) (5) Start address ((5) = ...
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Traces Traces are enabled in interrupt control mode 2. Trace mode is not activated in interrupt control mode 0, irrespective of the state of the T bit. For details of interrupt control modes, see section 5, Interrupt Controller. If ...
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Interrupts Interrupt exception handling can be requested by nine external sources (NMI, IRQ7 to IRQ0) and 52 internal sources in the on-chip supporting modules. Figure 4.3 classifies the interrupt sources and the number of interrupts of each type. The ...
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Trap Instruction Trap instruction exception handling starts when a TRAPA instruction is executed. Trap instruction exception handling can be executed at all times in the program execution state. The TRAPA instruction fetches a start address from a vector table ...
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Notes on Use of the Stack When accessing word data or longword data, the chip assumes that the lowest address bit is 0. The stack should always be accessed by word transfer instruction or longword transfer instruction, and the ...
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Section 5 Interrupt Controller 5.1 Overview 5.1.1 Features The chip controls interrupts by means of an interrupt controller. The interrupt controller has the following features. This chapter assumes the maximum number of interrupt sources available in these series—nine external interrupts ...
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Block Diagram A block diagram of the interrupt controller is shown in figure 5.1. INTM1 INTM0 SYSCR NMIEG NMI input NMI input unit IRQ input unit IRQ input ISCR Internal interrupt request SWDTEND to TEI Interrupt controller Legend: ISCR: ...
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Pin Configuration Table 5.1 summarizes the pins of the interrupt controller. Table 5.1 Interrupt Controller Pins Name Symbol Nonmaskable interrupt NMI IRQ7 to IRQ0 Input External interrupt requests 5.1.4 Register Configuration Table 5.2 summarizes the registers ...
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Register Descriptions 5.2.1 System Control Register (SYSCR) Bit : 7 — Initial value : 0 R/W : R/W SYSCR is an 8-bit readable/writable register that selects the interrupt control mode, and the detected edge for NMI. Only bits 5 ...
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Interrupt Priority Registers (IPRA to IPRK) Bit : 7 — Initial value : 0 R/W : — The IPR registers are eleven 8-bit readable/writable registers that set priorities (level for interrupts other than ...
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As shown in table 5.3, multiple interrupts are assigned to one IPR. Setting a value in the range from H'0 to H'7 in the 3-bit groups of bits and sets the priority of the ...
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IRQ Sense Control Registers H and L (ISCRH, ISCRL) ISCRH Bit : 15 IRQ7SCB IRQ7SCA IRQ6SCB IRQ6SCA IRQ5SCB IRQ5SCA IRQ4SCB IRQ4SCA Initial value : 0 R/W : R/W ISCRL Bit : 7 IRQ3SCB IRQ3SCA IRQ2SCB IRQ2SCA IRQ1SCB IRQ1SCA IRQ0SCB ...
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IRQ Status Register (ISR) Bit : 7 IRQ7F IRQ6F Initial value : 0 R/(W) * R/(W) * R/W : Note: * Only 0 can be written, to clear the flag. ISR is an 8-bit readable/writable register that indicates the ...
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Interrupt Sources Interrupt sources comprise external interrupts (NMI and IRQ7 to IRQ0) and internal interrupts (52 sources). 5.3.1 External Interrupts There are nine external interrupts: NMI and IRQ7 to IRQ0. NMI and IRQ7 to IRQ0 can be used to ...
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IRQnSCA, IRQnSCB Edge/level detection circuit IRQn input Note Figure 5.2 Block Diagram of Interrupts IRQ7 to IRQ0 Figure 5.3 shows the timing of setting IRQnF. φ IRQn input pin IRQnF The vector numbers for IRQ7 ...
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Internal Interrupts There are 52 sources for internal interrupts from on-chip supporting modules. • For each on-chip supporting module there are flags that indicate the interrupt request status, and enable bits that select enabling or disabling of these interrupts. ...
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Table 5.4 Interrupt Sources, Vector Addresses, and Interrupt Priorities Origin of Interrupt Interrupt Source Source Power-on reset Reserved Reserved for system use Trace Reserved for system use NMI External pin Trap instruction (4 sources) Reserved for system use IRQ External ...
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Origin of Interrupt Interrupt Source Source SWDTEND (software- DTC activated data transfer end) WOVI (interval timer) Watchdog timer CMI (compare match) Refresh controller Reserved — ADI (A/D conversion A/D end) Reserved — TGI0A (TGR0A input TPU capture/compare channel 0 match) ...
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Origin of Interrupt Interrupt Source Source TGI1A (TGR1A input TPU capture/compare channel 1 match) TGI1B (TGR1B input capture/compare match) TCI1V (overflow 1) TCI1U (underflow 1) TGI2A (TGR2A input TPU capture/compare channel 2 match) TGI2B (TGR2B input capture/compare match) TCI2V (overflow ...
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Origin of Interrupt Interrupt Source Source TGI4A (TGR4A input TPU capture/compare channel 4 match) TGI4B (TGR4B input capture/compare match) TCI4V (overflow 4) TCI4U (underflow 4) TGI5A (TGR5A input TPU capture/compare channel 5 match) TGI5B (TGR5B input capture/compare match) TCI5V (overflow ...
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Origin of Interrupt Interrupt Source Source DEND0A (channel DMAC 0/channel 0A transfer end) DEND0B (channel 0B transfer end) DEND1A (channel 1/channel 1A transfer end) DEND1B (channel 1B transfer end) Reserved — ERI0 (receive error 0) SCI channel 0 RXI0 (receive-data-full ...
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Interrupt Operation 5.4.1 Interrupt Control Modes and Interrupt Operation Interrupt operations in the chip differ depending on the interrupt control mode. NMI interrupts are accepted at all times except in the reset state and the hardware standby state. In ...
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Figure 5.4 shows a block diagram of the priority decision circuit. Interrupt source Figure 5.4 Block Diagram of Interrupt Control Operation Interrupt Acceptance Control: In interrupt control mode 0, interrupt acceptance is controlled by the I bit in CCR. Table ...
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Control: In interrupt control mode 2, 8-level mask level determination is performed for the selected interrupts in interrupt acceptance control according to the interrupt priority level (IPR). The interrupt source selected is the interrupt with the highest priority level, ...
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Interrupt Control Mode 0 Enabling and disabling of IRQ interrupts and on-chip supporting module interrupts can be set by means of the I bit in the CPU’s CCR. Interrupts are enabled when the I bit is cleared to 0, ...
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Program execution state Interrupt generated? Yes No IRQ0? Yes Save PC and CCR Read vector address Branch to interrupt handling routine Figure 5.5 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 0 No Yes NMI ...
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Interrupt Control Mode 2 Eight-level masking is implemented for IRQ interrupts and on-chip supporting module interrupts by comparing the interrupt mask level set by bits EXR in the CPU with IPR. Figure 5.6 shows a ...
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Program execution state Interrupt generated? Yes No Level 7 interrupt? Yes Level 6 interrupt? No Mask level 6 or below? Yes Save PC, CCR, and EXR Clear T bit to 0 Update mask level Read vector address Branch to interrupt ...
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Interrupt Exception Handling Sequence Figure 5.7 shows the interrupt exception handling sequence. The example shown is for the case where interrupt control mode 0 is set in advanced mode, and the program area and stack area are in on-chip ...
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Figure 5.7 Interrupt Exception Handling Rev.4.00 Sep. 07, 2007 Page 121 of 1210 REJ09B0245-0400 ...
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Interrupt Response Times The chip is capable of fast word transfer instruction to on-chip memory, and the program area is provided in on-chip ROM and the stack area in on-chip RAM, enabling high-speed processing. Table 5.9 shows interrupt response ...
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Usage Notes 5.5.1 Contention between Interrupt Generation and Disabling When an interrupt enable bit is cleared disable interrupts, the disabling becomes effective after execution of the instruction. In other words, when an interrupt enable bit is ...
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Instructions That Disable Interrupts Instructions that disable interrupts are LDC, ANDC, ORC, and XORC. After any of these instructions is executed, all interrupts including NMI are disabled and the next instruction is always executed. When the I bit is ...
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DTC and DMAC Activation by Interrupt 5.6.1 Overview The DTC and DMAC can be activated by an interrupt. In this case, the following options are available. 1. Interrupt request to CPU 2. Activation request to DTC 3. Activation request ...
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Block Diagram Figure 5.9 shows a block diagram of the DTC, DMAC, and interrupt controller. Interrupt request IRQ interrupt Interrupt source On-chip clear signal supporting module Interrupt controller Figure 5.9 Interrupt Control for DTC and DMAC Rev.4.00 Sep. 07, ...
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Operation The interrupt controller has three main functions in DTC and DMAC control. Selection of Interrupt Source: With the DMAC, the activation source is input directly to each channel. The activation source for each DMAC channel is selected with ...
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Table 5.11 Interrupt Source Selection and Clearing Control Settings DMAC DTA DTCE Legend: : The relevant interrupt is used. Interrupt source clearing is performed. (The CPU should clear the source flag in the interrupt handling ...
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Section 6 Bus Controller 6.1 Overview The chip has an on-chip bus controller (BSC) that manages the external address space divided into eight areas. The bus specifications, such as bus width and number of access states, can be set independently ...
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Idle cycle insertion ⎯ An idle cycle can be inserted in case of external read cycles in different areas ⎯ An idle cycle can be inserted in case of an external write cycle immediately after an external read cycle ...
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Block Diagram External bus control signals BREQ BACK BREQO WAIT External DRAM control signals Figure 6.1 Block Diagram of Bus Controller Area decoder ABWCR ASTCR BCRH BCRL Bus controller Wait controller WCRH WCRL DRAM ...
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Pin Configuration Table 6.1 summarizes the pins of the bus controller. Table 6.1 Bus Controller Pins Name Symbol AS Address strobe RD Read HWR High write/write enable LWR Low write CS Chip select 0 CS Chip select 1 CS ...
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Name Symbol WAIT Wait BREQ Bus request BACK Bus request acknowledge BREQO Bus request output 6.1.4 Register Configuration Table 6.2 summarizes the registers of the bus controller. Table 6.2 Bus Controller Registers Name Bus width control register Access state control ...
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Register Descriptions 6.2.1 Bus Width Control Register (ABWCR) Bit : 7 ABW7 ABW6 Modes Initial value : 1 R/W : R/W Mode 4 Initial value : 0 R/W : R/W ABWCR is an 8-bit readable/writable register ...
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Access State Control Register (ASTCR) Bit : 7 AST7 AST6 Initial value : 1 R/W : R/W ASTCR is an 8-bit readable/writable register that designates each area as either 2-state access space or 3-state access space. ASTCR sets the ...
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WCRH Bit : 7 W71 Initial value : 1 R/W : R/W Bits 7 and 6—Area 7 Wait Control 1 and 0 (W71, W70): These bits select the number of program wait states when area 7 in external space is ...
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Bits 3 and 2—Area 5 Wait Control 1 and 0 (W51, W50): These bits select the number of program wait states when area 5 in external space is accessed while the AST5 bit in ASTCR is set to 1. Bit ...
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WCRL Bit : 7 W31 Initial value : 1 R/W : R/W Bits 7 and 6—Area 3 Wait Control 1 and 0 (W31, W30): These bits select the number of program wait states when area 3 in external space is ...
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Bits 3 and 2—Area 1 Wait Control 1 and 0 (W11, W10): These bits select the number of program wait states when area 1 in external space is accessed while the AST1 bit in ASTCR is set to 1. Bit ...
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Bus Control Register H (BCRH) Bit : 7 ICIS1 ICIS0 Initial value : 1 R/W : R/W BCRH is an 8-bit readable/writable register that selects enabling or disabling of idle cycle insertion, and the memory interface for areas 2 ...
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Bit 4—Burst Cycle Select 1 (BRSTS1): Selects the number of burst cycles for the burst ROM interface. Bit 4 BRSTS1 Description 0 Burst cycle comprises 1 state 1 Burst cycle comprises 2 states Bit 3—Burst Cycle Select 0 (BRSTS0): Selects ...
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Bus Control Register L (BCRL) Bit : 7 BRLE BREQOE Initial value : 0 R/W : R/W BCRL is an 8-bit readable/writable register that performs selection of the external bus-released state protocol, selection of the area partition unit, enabling ...
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Bit 5 EAE H8S/2339, H8S/2338 0 On-chip ROM 1 Addresses H'010000 to H'03FFFF are external addresses in external expanded mode or reserved area * 1 Notes not access a reserved area. 2. Addresses H'010000 to H'05FFFF in the ...
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Memory Control Register (MCR) Bit : 7 TPC Initial value : 0 R/W : R/W MCR is an 8-bit readable/writable register that selects the DRAM strobe control method, number of precharge cycles, access mode, address multiplexing shift size, and ...
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Bit 4—Reserved: Only 1 should be written to this bit. Bits 3 and 2—Multiplex Shift Count 1 and 0 (MXC1, MXC0): These bits select the size of the shift toward the lower half of the row address in row address/column ...
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DRAM Control Register (DRAMCR) Bit : 7 RFSHE RCW Initial value : 0 R/W : R/W DRAMCR is an 8-bit readable/writable register that selects the DRAM refresh mode and refresh counter clock and controls the refresh timer. DRAMCR is ...
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Bit 4—Compare Match Flag (CMF): Status flag that indicates a match between the values of RTCNT and RTCOR. When refresh control is performed (RFSHE = 1), 1 should be written to the CMF bit when writing to DRAMCR. Bit 4 ...
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Refresh Timer Counter (RTCNT) Bit : 7 Initial value : 0 R/W : R/W RTCNT is an 8-bit readable/writable up-counter. RTCNT counts up using the internal clock selected by bits CKS2 to CKS0 in DRAMCR. When RTCNT matches RTCOR ...
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Overview of Bus Control 6.3.1 Area Partitioning In advanced mode, the bus controller partitions the 16-Mbyte address space into eight areas 2-Mbyte units, and performs bus control for external space in area units. Figure 6.2 ...
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Bus Specifications The external space bus specifications consist of three elements: (1) bus width, (2) number of access states, and (3) number of program wait states. The bus width and number of access states for on-chip memory and internal ...
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Table 6.3 Bus Specifications for Each Area (Basic Bus Interface) ABWCR ASTCR WCRH, WCRL ABWn ASTn Wn1 0 0 — — 6.3.3 Memory Interfaces The chip’s interfaces comprise a basic bus interface ...
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Advanced Mode The initial state of each area is basic bus interface, 3-state access space. The initial bus width is selected according to the operating mode. The bus specifications described here cover basic items only, and the sections on ...
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Chip Select Signals The chip can output chip select signals (CS when the corresponding external space area is accessed. Figure 6.3 shows an example of CS Enabling or disabling (DDR) bit for the port corresponding to ...
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Basic Bus Interface 6.4.1 Overview The basic bus interface enables direct connection of ROM, SRAM, and so on. The bus specifications can be selected with ABWCR, ASTCR, WCRH, and WCRL. (See table 6.3.) 6.4.2 Data Size and Data Alignment ...
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Access Space: Figure 6.5 illustrates data alignment control for the 16-bit access space. With the 16-bit access space, the upper data bus (D for accesses. The amount of data that can be accessed at one time is one byte ...
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Valid Strobes Table 6.4 shows the data buses used and valid strobes for the access spaces read, the RD signal is valid without discrimination between the upper and lower halves of the data bus write, ...
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Basic Timing 8-Bit 2-State Access Space: Figure 6.6 shows the bus timing for an 8-bit 2-state access space. When an 8-bit access space is accessed, the upper half (D The LWR pin is fixed high. Wait states cannot be ...
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Access Space: Figure 6.7 shows the bus timing for an 8-bit 3-state access space. When an 8-bit access space is accessed, the upper half (D The LWR pin is fixed high. Wait states can be inserted. φ Address ...
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Access Space: Figures 6.8 to 6.10 show bus timings for a 16-bit 2-state access space. When a 16-bit access space is accessed, the upper half (D the even address, and the lower half (D Wait states cannot be ...
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Address bus Read HWR LWR Write Note Figure 6.9 Bus Timing for 16-Bit 2-State Access Space (2) (Odd ...
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Address bus CSn Read HWR LWR Write Note Figure 6.10 Bus Timing ...
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Access Space: Figures 6.11 to 6.13 show bus timings for a 16-bit 3-state access space. When a 16-bit access space is accessed , the upper half (D for the even address, and the lower half (D Wait states ...
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Address bus CSn Read HWR LWR Write Note Figure 6.12 Bus Timing ...
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Address bus CSn Read HWR LWR Write Note Figure 6.13 Bus Timing ...
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Wait Control When accessing external space, the chip can extend the bus cycle by inserting one or more wait states (T ). There are two ways of inserting wait states: program wait insertion and pin wait w insertion using ...
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WAIT Address bus AS RD Read Data bus HWR, LWR Write Data bus Note: Downward arrows indicates the timing of WAIT pin sampling. Figure 6.14 Example of Wait State Insertion Timing The settings after a reset are: 3-state access, ...
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DRAM Interface 6.5.1 Overview When the chip is in advanced mode, external space areas can be designated as DRAM space, and DRAM interfacing performed. With the DRAM interface, DRAM can be directly connected to the chip. ...
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Address Multiplexing With DRAM space, the row address and column address are multiplexed. In address multiplexing, the size of the shift of the row address is selected with bits MXC1 and MXC0 in MCR. Table 6.5 shows the relation ...