HD64F2338VFC25 Renesas Electronics America, HD64F2338VFC25 Datasheet - Page 849
![MCU 3V 256K 144-QFP](/photos/12/30/123043/df2633f25v_sml.jpg)
HD64F2338VFC25
Manufacturer Part Number
HD64F2338VFC25
Description
MCU 3V 256K 144-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheet
1.DF2338VFC25V.pdf
(1246 pages)
Specifications of HD64F2338VFC25
Core Processor
H8S/2000
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
106
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 4x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
144-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD64F2338VFC25
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Notes: 1. Data transfer is performed by byte transfer. The lower 8 bits of the first
Program Data Operation Chart
5. A write pulse of (z1) or (z2) μs should be applied according to the progress
6. For the values of x, y, z1, z2, z3, α, β, γ, ε, η, θ, and N, see section 22.2.6, Flash Memory Characteristics.
2. Verify data is read in 16-bit (W) units.
3. Even bits for which programming has been completed in the 128-byte
4. A 128-byte area for storing program data, a 128-byte area for storing
Original Data
Note 7: Write Pulse Width
Note: Use a (z3) µs write pulse for additional
Number of Writes (n)
address written to must be H'00 or H'80. A 128-byte data transfer must
be performed even if writing fewer than 128 bytes; in this case, H'FF
data must be written to the extra addresses.
programming loop will be subjected to additional programming if they fail
the subsequent verify operation.
reprogram data, and a 128-byte area for storing additional program data
should be provided in RAM. The contents of the reprogram data and
additional program data areas are modified as programming proceeds.
of programming. See note 7 for the pulse widths. When the additional program
data is programmed, a write pulse of (z3) μs should be applied. Reprogram data X' stands for reprogram data to which a write pulse has been applied.
Additional program data
Write pulse application subroutine
Reprogram data area
Wait (z1) μs or (z2) μs or (z3) μs
(D)
Program data area
0
1
area (128 bytes)
Clear PSU bit in FLMCR1
programming.
Set PSU bit in FLMCR1
Sub-routine write pulse
Clear P bit in FLMCR1
(128 bytes)
(128 bytes)
1000
Set P bit in FLMCR1
998
999
10
11
12
13
1
2
3
4
5
6
7
8
9
.
.
.
RAM
Disable WDT
Enable WDT
Verify Data
Wait (y) μs
Wait (α) μs
Wait (β) μs
End sub
(V)
0
1
0
1
Reprogram Data
Write Time (z) μs
Figure 19.41 Program/Program-Verify Flowchart
*6
(X)
z1
z1
z1
z1
z1
z1
z2
z2
z2
z2
z2
z2
z2
z2
z2
z2
1
0
1
.
.
.
*6
*5 *6
*6
*6
Programming completed
Programming incomplete; reprogram
Still in erased state; no action
Increment address
Comments
Store 128-byte program data in program
NG
data area consecutively to flash memory
additional program data area in RAM to
Write 128-byte data in RAM reprogram
Transfer reprogram data to reprogram
Additional program data computation
H'FF dummy write to verify address
data area and reprogram data area
Transfer additional program data to
Sequentially write 128-byte data in
Reprogram data computation
additional program data area
(z3) µs additional write pulse
Clear SWE bit in FLMCR1
Additional Program Data Operation Chart
Set SWE bit in FLMCR1
Clear PV bit in FLMCR1
Set PV bit in FLMCR1
Reprogram
Start of programming
End of programming
Data (X')
Read data = verify
Read verify data
(z1) μs or (z2) μs
data verification
flash memory
Write Pulse
0
1
Wait (x) μs
Wait (γ) μs
Wait (ε) μs
completed?
Write pulse
Wait (η) μs
Wait (θ) μs
data area
128-byte
6 ≥ n ?
6 ≥ n ?
m = 0?
m = 0
n = 1
data?
Start
Rev.4.00 Sep. 07, 2007 Page 817 of 1210
OK
OK
Verify Data
OK
OK
OK
Sub-routine-call
(V)
0
1
0
1
NG
NG
NG
Program Data (Y)
NG
Additional
*6
*6
*4
*1
See note 7 for pulse width
*6
*6
*6
*2
*4
*3
*4
*6
*1
*6
0
1
Perform programming in the erased state.
Do not perform additional programming
on previously programmed addresses.
m = 1
Clear SWE bit in FLMCR1
Programming failure
Additional programming executed
Additional programming not executed
Additional programming not executed
Additional programming not executed
Wait (θ) μs
n ≥ N?
OK
Comments
*6
REJ09B0245-0400
NG
n ← n + 1
*6
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