HD64F2338VFC25 Renesas Electronics America, HD64F2338VFC25 Datasheet - Page 17
![MCU 3V 256K 144-QFP](/photos/12/30/123043/df2633f25v_sml.jpg)
HD64F2338VFC25
Manufacturer Part Number
HD64F2338VFC25
Description
MCU 3V 256K 144-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheet
1.DF2338VFC25V.pdf
(1246 pages)
Specifications of HD64F2338VFC25
Core Processor
H8S/2000
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
106
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 4x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
144-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD64F2338VFC25
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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6.6
6.7
6.8
6.9
6.10 Bus Release....................................................................................................................... 194
6.11 Bus Arbitration.................................................................................................................. 197
6.12 Resets and Bus Controller................................................................................................. 199
Section 7 DMA Controller
7.1
7.2
6.5.7
6.5.8
6.5.9
6.5.10 Burst Operation.................................................................................................... 176
6.5.11 Refresh Control.................................................................................................... 179
DMAC Single Address Mode and DRAM Interface ........................................................ 183
6.6.1
6.6.2
Burst ROM Interface......................................................................................................... 185
6.7.1
6.7.2
6.7.3
Idle Cycle .......................................................................................................................... 188
6.8.1
6.8.2
Write Data Buffer Function .............................................................................................. 193
6.10.1 Overview.............................................................................................................. 194
6.10.2 Operation ............................................................................................................. 194
6.10.3 Pin States in External-Bus-Released State ........................................................... 195
6.10.4 Transition Timing ................................................................................................ 196
6.10.5 Usage Note........................................................................................................... 197
6.11.1 Overview.............................................................................................................. 197
6.11.2 Operation ............................................................................................................. 197
6.11.3 Bus Transfer Timing ............................................................................................ 198
6.11.4 External Bus Release Usage Note........................................................................ 198
Overview........................................................................................................................... 201
7.1.1
7.1.2
7.1.3
7.1.4
7.1.5
Register Descriptions (1) (Short Address Mode) .............................................................. 207
7.2.1
7.2.2
7.2.3
Precharge State Control ....................................................................................... 171
Wait Control ........................................................................................................ 172
Byte Access Control ............................................................................................ 174
When DDS = 1..................................................................................................... 183
When DDS = 0..................................................................................................... 184
Overview.............................................................................................................. 185
Basic Timing........................................................................................................ 185
Wait Control ........................................................................................................ 187
Operation ............................................................................................................. 188
Pin States in Idle Cycle ........................................................................................ 192
Features................................................................................................................ 201
Block Diagram..................................................................................................... 202
Overview of Functions......................................................................................... 203
Pin Configuration................................................................................................. 205
Register Configuration......................................................................................... 206
Memory Address Registers (MAR) ..................................................................... 208
I/O Address Register (IOAR) .............................................................................. 209
Execute Transfer Count Register (ETCR) ........................................................... 209
................................................................................................ 201
Rev.4.00 Sep. 07, 2007 Page xv of xxx
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