HD64F2338VFC25 Renesas Electronics America, HD64F2338VFC25 Datasheet - Page 217

• Manufacturer Part Number: HD64F2338VFC25
• Description: MCU 3V 256K 144-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of HD64F2338VFC25

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 106
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 4x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

6.7
6.7.1
With the chip, external space area 0 can be designated as burst ROM space, and burst ROM
interfacing performed. The burst ROM space interface enables 16-bit ROM with burst access
capability to be accessed at high speed.
Area 0 can be designated as burst ROM space by means of the BRSTRM bit in BCRH.
Consecutive burst accesses of a maximum or 4 words or 8 words can be performed for CPU
instruction fetches only. One or two states can be selected for burst access.
6.7.2
The number of states in the initial cycle (full access) of the burst ROM interface is determined by
the setting of the AST0 bit in ASTCR. When the AST0 bit is set to 1, wait state insertion is also
possible. One or two states can be selected for the burst cycle, according to the setting of the
BRSTS1 bit in BCRH. Wait states cannot be inserted. When area 0 is designated as burst ROM
space, it functions as 16-bit access space regardless of the setting of the ABW0 bit in ABWCR.
When the BRSTS0 bit in BCRH is cleared to 0, burst access of up to 4 words is performed; when
the BRSTS0 bit is set to 1, burst access of up to 8 words is performed.
The basic access timing for burst ROM space is shown in figures 6.30 (a) and (b). The timing
shown in figure 6.30 (a) is for the case where the AST0 and BRSTS1 bits are both set to 1, and
that in figure 6.30 (b) is for the case where both these bits are cleared to 0.
Burst ROM Interface
Overview
Basic Timing
Rev.4.00 Sep. 07, 2007 Page 185 of 1210
REJ09B0245-0400