HD64F2338VFC25 Renesas Electronics America, HD64F2338VFC25 Datasheet - Page 86
![MCU 3V 256K 144-QFP](/photos/12/30/123043/df2633f25v_sml.jpg)
HD64F2338VFC25
Manufacturer Part Number
HD64F2338VFC25
Description
MCU 3V 256K 144-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheet
1.DF2338VFC25V.pdf
(1246 pages)
Specifications of HD64F2338VFC25
Core Processor
H8S/2000
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
106
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 4x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
144-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD64F2338VFC25
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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(4) Register Indirect with Post-Increment or Pre-Decrement—@ERn+ or @-ERn:
• Register indirect with post-increment—@ERn+
• Register indirect with pre-decrement—@-ERn
(5) Absolute Address—@aa:8, @aa:16, @aa:24, or @aa:32: The instruction code contains the
absolute address of a memory operand. The absolute address may be 8 bits long (@aa:8), 16 bits
long (@aa:16), 24 bits long (@aa:24), or 32 bits long (@aa:32).
To access data, the absolute address should be 8 bits (@aa:8), 16 bits (@aa:16), or 32 bits
(@aa:32) long. For an 8-bit absolute address, the upper 24 bits are all assumed to be 1 (H'FFFF).
For a 16-bit absolute address the upper 16 bits are a sign extension. A 32-bit absolute address can
access the entire address space.
A 24-bit absolute address (@aa:24) indicates the address of a program instruction. The upper 8
bits are all assumed to be 0 (H'00).
Table 2.5 indicates the accessible absolute address ranges.
Table 2.5
Absolute Address
Data address
Program instruction address
Rev.4.00 Sep. 07, 2007 Page 54 of 1210
REJ09B0245-0400
The register field of the instruction code specifies an address register (ERn) which contains the
address of a memory operand. After the operand is accessed, 1, 2, or 4 is added to the address
register contents and the sum is stored in the address register. The value added is 1 for byte
access, 2 for word transfer instruction, or 4 for longword transfer instruction. For word or
longword transfer instruction, the register value should be even.
The value 1, 2, or 4 is subtracted from an address register (ERn) specified by the register field
in the instruction code, and the result becomes the address of a memory operand. The result is
also stored in the address register. The value subtracted is 1 for byte access, 2 for word transfer
instruction, or 4 for longword transfer instruction. For word or longword transfer instruction,
the register value should be even.
Absolute Address Access Ranges
16 bits (@aa:16)
32 bits (@aa:32)
24 bits (@aa:24)
8 bits (@aa:8)
Advanced Mode
H'FFFF00 to H'FFFFFF
H'000000 to H'007FFF,
H'FF8000 to H'FFFFFF
H'000000 to H'FFFFFF
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