DF2161BVTE10 Renesas Electronics America, DF2161BVTE10 Datasheet - Page 610
DF2161BVTE10
Manufacturer Part Number
DF2161BVTE10
Description
MCU 3V 128K 144-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheet
1.DF2160BVT10V.pdf
(847 pages)
Specifications of DF2161BVTE10
Core Processor
H8S/2000
Core Size
16-Bit
Speed
10MHz
Connectivity
Host Interface (LPC), I²C, IrDA, SCI, X-Bus
Peripherals
PWM, WDT
Number Of I /o
114
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
144-TQFP, 144-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
HD64F2161BVTE10
HD64F2161BVTE10
HD64F2161BVTE10
- Current page: 610 of 847
- Download datasheet (5Mb)
Section 19 Host Interface LPC Interface (LPC)
Bit
4
3
Rev. 3.00 Mar 21, 2006 page 554 of 788
REJ09B0300-0300
Bit Name Initial Value Slave Host Description
SMIE3B
SMIE3A
0
0
R/W
R/W
R/W
—
—
Host SMI Interrupt Enable 3B
Enables or disables a host SMI interrupt request
when OBF3B is set by a TWR15 write.
0: Host SMI interrupt request by OBF3B and
SMIE3B is disabled
[Clearing conditions]
1: [When IEDIR = 0]
[Setting condition]
Writing 1 after reading SMIE3B = 0
Host SMI Interrupt Enable 3A
Enables or disables a host SMI interrupt request
when OBF3A is set by an ODR3 write.
0: Host SMI interrupt request by OBF3A and
SMIE3A is disabled
[Clearing conditions]
1: [When IEDIR = 0]
[Setting condition]
Writing 1 after reading SMIE3A = 0
Writing 0 to SMIE3B
LPC hardware reset, LPC software reset
Clearing OBF3B to 0 (when IEDIR = 0)
Host SMI interrupt request by setting OBF3B to 1
is enabled
[When IEDIR = 1]
Host SMI interrupt is requested
Writing 0 to SMIE3A
LPC hardware reset, LPC software reset
Clearing OBF3A to 0 (when IEDIR = 0)
Host SMI interrupt request by setting OBF3A to 1
is enabled
[When IEDIR = 1]
Host SMI interrupt is requested
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