UPD70F3765GF-GAT-AX Renesas Electronics America, UPD70F3765GF-GAT-AX Datasheet - Page 1009

• Manufacturer Part Number: UPD70F3765GF-GAT-AX
• Description: MCU 32BIT V850ES/JX3-H 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Hr

Specifications of UPD70F3765GF-GAT-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 48MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3-H, V850ES/JH3-H
20.15 Baud Rate Settings
20.15.1 Bit rate setting conditions
follows.
R01UH0042EJ0400 Rev.4.00
Sep 30, 2010
Make sure that the settings are within the range of limit values for ensuring correct operation of the CAN controller, as
Remark
Table 20-22 shows the combinations of bit rates that satisfy the above conditions.
(a) 5TQ ≤ SPT (sampling point) ≤ 17 TQ
(b) 8 TQ ≤ DBT (data bit time) ≤ 25 TQ
(c) 1 TQ ≤ SJW (synchronization jump width) ≤ 4TQ
(d) 4TQ ≤ TSEG1 ≤ 16TQ [3 ≤ Setting value of TSEG1[3:0] ≤ 15]
(e) 1TQ ≤ TSEG2 ≤ 8TQ [0 ≤ Setting value of TSEG2[2:0] ≤ 7]
SPT = TSEG1 + 1TQ
DBT = TSEG1 + TSEG2 + 1TQ = TSEG2 + SPT
SJW ≤ DBT – SPT
TQ = 1/f
TSEG1[3:0] (C0BTR.TSEG13 to C0BTR.TSEG10 bits)
TSEG2[2:0] (C0BTR.TSEG22 to C0BTR.TSEG20 bits)
TQ
(f
TQ
: CAN protocol layer base system clock)
CHAPTER 20 CAN CONTROLLER
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