UPD70F3765GF-GAT-AX Renesas Electronics America, UPD70F3765GF-GAT-AX Datasheet - Page 208

• Manufacturer Part Number: UPD70F3765GF-GAT-AX
• Description: MCU 32BIT V850ES/JX3-H 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Hr

Specifications of UPD70F3765GF-GAT-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 48MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Note Lockup time
Remark
V850ES/JG3-H, V850ES/JH3-H
6.4
6.4.1
6.4.2
register of port CM.
when it is in the operable status. It outputs a low level in the stopped status. However, the CLKOUT pin is in the port
mode (PCM1 pin: input mode) after reset and until it is set in the output mode. Therefore, the status of the pin is Hi-Z.
R01UH0042EJ0400 Rev.4.00
Sep 30, 2010
Target Clock
Subclock oscillator (f
CPU clock (f
Internal system clock (f
Main clock (in PLL mode, f
Peripheral clock (f
WT clock (main)
WT clock (sub)
WDT2 clock (internal oscillation)
WDT2 clock (main)
WDT2 clock (sub)
Main clock oscillator (f
The following table shows the operation status of each clock.
The clock output function is used to output the internal system clock (f
The internal system clock (f
The CLKOUT pin functions alternately as the PCM1 pin and functions as a clock output pin if so specified by the control
The status of the CLKOUT pin is the same as the internal system clock in Table 6-1 and the pin can output the clock
Operation
Operation of each clock
Clock output function
×: Stopped
CPU
: Operable
Register Setting and
)
XX
Operation Status
to f
XT
)
CLK
X
XX
)
/1,024)
)
XX
)
CLK
) is selected by using the PCC.CK3 to PCC.CK0 bits.
During
Reset
×
×
×
×
×
×
×
×
Table 6-1. Operation Status of Each Clock
Stabilization
Time Count
Oscillation
During
CLK Bit = 0, MCK Bit = 0
×
×
Note
×
×
HALT
Mode
×
IDLE1,
IDLE2
Mode
×
×
×
×
×
CHAPTER 6 CLOCK GENERATION FUNCTION
PCC Register
STOP
Mode
CLK
×
×
×
×
×
×
×
) from the CLKOUT pin.
Subclock
Mode
CLS Bit = 1,
MCK Bit = 0
Sub-IDLE
Mode
×
×
×
×
Subclock
Mode
CLS Bit = 1,
MCK Bit = 1
×
×
×
×
×
Page 208 of 1509
Sub-IDLE
Mode
×
×
×
×
×
×
×