UPD70F3765GF-GAT-AX Renesas Electronics America, UPD70F3765GF-GAT-AX Datasheet - Page 462

• Manufacturer Part Number: UPD70F3765GF-GAT-AX
• Description: MCU 32BIT V850ES/JX3-H 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Hr

Specifications of UPD70F3765GF-GAT-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 48MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3-H, V850ES/JH3-H
R01UH0042EJ0400 Rev.4.00
Sep 30, 2010
(1) Basic counter operation
This section explains the basic operation of the 16-bit counter. For details, refer to the description of the operation
in each mode.
(a) Count start operation
(b) Clear operation
(c) Overflow operation
• Encoder compare mode
• Triangular-wave PWM mode
• Mode other than above
The 16-bit counter is cleared to 0000H when its value matches the value of the compare register, when its
value is captured, when the edge of the encoder clear signal is detected, and when the clear level condition of
the TENC00, TENC01, and TECR0 pins is detected. The count operation from FFFFH to 0000H that takes
place immediately after the counter has started counting or when the counter overflows is not a clear operation.
Therefore, the INTTT0CC0 and INTTT0CC1 interrupt signals are not generated.
The 16-bit counter overflows when it counts up from FFFFH to 0000H in the free-running mode, pulse width
measurement mode, and encoder compare mode. If the counter overflows in the free-running mode and pulse
width measurement mode, the TT0OPT0.TT0OVF bit is set to 1 and an interrupt request signal (INTTT0OV) is
generated.
If the counter overflows in the encoder compare mode, the TT0OPT1.TT0EOF bit is set to 1 and an interrupt
request signal (INTTT0OV) is generated.
Note that the INTTT0OV signal is not generated under the following conditions.
• Immediately after a count operation has been started
• If the counter value matches the compare value FFFFH and is cleared
• When FFFFH is captured and cleared to 0000H in the pulse width measurement mode
Caution After the overflow interrupt request signal (INTTT0OV) has been generated, be sure to check
A count operation is controlled by TENC00 and TENC01 phases.
The 16-bit counter initial setting is performed by transferring the set value of the TT0TCW register to the 16-
bit counter and the count operation is started. (When the TT0CTL2.TT0ECC bit = 0, the TT0TCW register set
value is transferred to the 16-bit counter at the timing when the TT0CTL0.TT0CE bit changes from 0 to 1.)
The 16-bit counter starts counting from the initial value FFFFH.
It counts up FFFFH, 0000H, 0001H, 0002H, 0003H, and so on.
Following the count-up operation, the counter counts down upon a match between the 16-bit count value and
the CCR0 buffer register.
The 16-bit counter starts counting from the initial value FFFFH.
It counts up FFFFH, 0000H, 0001H, 0002H, 0003H, and so on.
that the overflow flag (TT0OVF, TT0EOF bits) is set to 1.
CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT)
Page 462 of 1509