UPD70F3765GF-GAT-AX Renesas Electronics America, UPD70F3765GF-GAT-AX Datasheet - Page 744

• Manufacturer Part Number: UPD70F3765GF-GAT-AX
• Description: MCU 32BIT V850ES/JX3-H 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Hr

Specifications of UPD70F3765GF-GAT-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 48MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3-H, V850ES/JH3-H
17.6.4 SBF reception
bit to 1.
detection is performed.
interrupt request signal (INTUCnR) is output. The UCnOPT0.UCnSRF bit is automatically cleared and SBF reception ends.
Error detection for the UCnSTR.UCnOVE, UCnSTR.UCnPE, and UCnSTR.UCnFE bits is suppressed and UART
communication error detection processing is not performed. Moreover, data transfer of the UARTCn reception shift
register and UCnRX register is not performed and FFH, the initial value, is held. If the SBF width is 10 or fewer bits,
reception is terminated as error processing without outputting an interrupt, and the SBF reception mode is returned to.
The UCnSRF bit is not cleared at this time.
R01UH0042EJ0400 Rev.4.00
Sep 30, 2010
The reception wait status is entered by setting the UCnCTL0.UCnPWR bit to 1 and then setting the UCnCTL0.UCnRXE
The SBF reception wait status is set by setting the SBF reception trigger (UCnOPT0.UCnSRT bit) to 1.
In the SBF reception wait status, similarly to the UART reception wait status, the RXDCn pin is monitored and start bit
Following detection of the start bit, reception is started and the internal counter counts up according to the set baud rate.
When a stop bit is received, if the SBF width is 11 or more bits, normal processing is judged and a reception completion
Cautions 1. If SBF is transmitted during a data reception, a framing error occurs.
(a) Normal SBF reception (detection of stop bit in more than 10.5 bits)
(b) SBF reception error (detection of stop bit in 10.5 or fewer bits)
2. Do not set the SBF reception trigger bit (UCnSRT) and SBF transmission trigger bit (UCnSTT) to 1
during an SBF reception (UCnSRF = 1).
INTUCnR
interrupt
RXDCn
UCnSRF
RXDCn
UCnSRF
INTUCnR
interrupt
1
CHAPTER 17 ASYNCHRONOUS SERIAL INTERFACE C (UARTC)
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Figure 17-11. SBF Reception
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11.5
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10.5
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