UPD70F3765GF-GAT-AX Renesas Electronics America, UPD70F3765GF-GAT-AX Datasheet - Page 950

• Manufacturer Part Number: UPD70F3765GF-GAT-AX
• Description: MCU 32BIT V850ES/JX3-H 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Hr

Specifications of UPD70F3765GF-GAT-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 48MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3-H, V850ES/JH3-H
R01UH0042EJ0400 Rev.4.00
Sep 30, 2010
(6) CAN0 module control register (C0CTRL)
(a) Read
(b) Write
(a) Read
Remark
Remark • The TSTAT bit is set to 1 under the following conditions (timing)
The C0CTRL register is used to control the operation mode of the CAN module.
After reset: 0000H
C0CTRL
C0CTRL
RSTAT
TSTAT
0
1
0
1
• The RSTAT bit is set to 1 under the following conditions (timing)
• The RSTAT bit is cleared to 0 under the following conditions (timing)
•
•
•
•
The SOF bit of a receive frame is detected
On occurrence of arbitration loss during a transmit frame
When a recessive level is detected at the second bit of the interframe space
On transition to the initialization mode at the first bit of the interframe space
• The TSTAT bit is cleared to 0 under the following conditions (timing)
•
•
•
•
•
Transmission is stopped.
Transmission is in progress.
Reception is stopped.
Reception is in progress.
The SOF bit of a transmit frame is detected
During transition to bus-off status
On occurrence of arbitration loss in transmit frame
On detection of recessive level at the second bit of the interframe space
On transition to the initialization mode at the first bit of the interframe space
CCERC
CCERC
Set
15
15
0
7
7
0
R/W
Clear
Set
Address: 03FEC050H
AL
AL
AL
14
14
0
6
6
VALID
VALID
Clear
13
13
0
5
0
5
Transmission status bit
Reception status bit
PSMODE
PSMODE
PSMODE
Clear
Set
12
12
0
4
1
1
4
1
PSMODE
PSMODE
PSMODE
Clear
Set
11
11
0
3
0
0
3
0
CHAPTER 20 CAN CONTROLLER
OPMODE
OPMODE
OPMODE
Clear
Set
10
10
0
2
2
2
2
2
OPMODE
OPMODE
OPMODE
RSTAT
Clear
Set
9
1
1
9
1
1
1
OPMODE
OPMODE
OPMODE
Page 950 of 1509
TSTAT
Clear
Set
8
0
0
8
0
0
0
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