UPD70F3765GF-GAT-AX Renesas Electronics America, UPD70F3765GF-GAT-AX Datasheet - Page 447

• Manufacturer Part Number: UPD70F3765GF-GAT-AX
• Description: MCU 32BIT V850ES/JX3-H 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Hr

Specifications of UPD70F3765GF-GAT-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 48MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3-H, V850ES/JH3-H
R01UH0042EJ0400 Rev.4.00
Sep 30, 2010
(6) TMT0 I/O control register 2 (TT0IOC2)
The TT0IOC2 register is an 8-bit register that controls the valid edge for the external event count input signal
(EVTT0 pin) and external trigger input signal (EVTT0 pin).
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 00H.
TT0IOC2
After reset: 00H
Cautions 1. Rewrite the TT0EES1, TT0EES0, TT0ETS1, and TT0ETS0 bits when the
TT0EES1
TT0ETS1
0
0
1
1
0
0
1
1
0
7
R/W
TT0EES0
TT0ETS0
2. The TT0EES1 and TT0EES0 bits are valid only when the
3. The TT0ETS1 and TT0ETS0 bits are valid only in the external trigger
6
0
0
1
0
1
0
1
0
1
TT0CTL0.TT0CE bit = 0. (The same value can be written when the
TT0CE bit = 1.)
TT0CE bit to 0 and then set the bits again.
TT0CTL1.TT0EEE bit = 1 or when the external event count mode (the
TT0CTL1.TT0MD3 to TT0CTL1.TT0MD0 bits = 0001) has been set.
pulse mode or one-shot pulse output mode.
Address: FFFFF605H
External event count input signal (EVTT0 pin) valid edge setting
No edge detection (external event count invalid)
Detection of rising edge
Detection of falling edge
Detection of both edges
No edge detection (external trigger invalid)
Detection of rising edge
Detection of falling edge
Detection of both edges
External trigger input signal (EVTT0 pin) valid edge setting
5
0
CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT)
4
0
If rewriting was mistakenly performed, clear the
TT0EES1 TT0EES0 TT0ETS1 TT0ETS0
3
2
1
0
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