UPD70F3765GF-GAT-AX Renesas Electronics America, UPD70F3765GF-GAT-AX Datasheet - Page 290

• Manufacturer Part Number: UPD70F3765GF-GAT-AX
• Description: MCU 32BIT V850ES/JX3-H 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Hr

Specifications of UPD70F3765GF-GAT-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 48MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3-H, V850ES/JH3-H
R01UH0042EJ0400 Rev.4.00
Sep 30, 2010
TAAnIOC1
TAAnIOC2
TAAnOPT0
(d) TAAn I/O control register 1 (TAAnIOC1)
(e) TAAn I/O control register 2 (TAAnIOC2)
(f) TAAn option register 0 (TAAnOPT0)
(g) TAAn counter read buffer register (TAAnCNT)
(h) TAAn capture/compare registers 0 and 1 (TAAnCCR0 and TAAnCCR1)
The value of the 16-bit counter can be read by reading the TAAnCNT register.
These registers function as capture registers or compare registers depending on the setting of the
TAAnOPT0.TAAnCCSm bit.
When the registers function as capture registers, they store the count value of the 16-bit counter when
the valid edge input to the TIAAnm pin is detected.
When the registers function as compare registers and when D
INTTAAnCCm signal is generated when the counter reaches (D
TOAAnm pin is inverted.
Remark
0
0
0
n = 0 to 3, 5
m = 0, 1
Figure 7-36. Register Setting in Free-Running Timer Mode (2/2)
0
0
0
TAAnCCS1
0/1
0
0
TAAnCCS0
0/1
0
0
TAAnEES1
TAAnIS3
CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA)
0/1
0/1
0
TAAnEES0 TAAnETS1 TAAnETS0
TAAnIS2 TAAnIS1 TAAnIS0
0/1
0/1
0
0/1
0
0
m
is set to the TAAnCCRm register, the
m
+ 1), and the output signal of the
TAAnOVF
0/1
0/1
0
Select valid edge of
external event count input
Select valid edge
of TIAAn0 pin input
Select valid edge
of TIAAn1 pin input
Overflow flag
Specifies if TAAnCCR0
register functions as
capture or compare register
Specifies if TAAnCCR1
register functions as
capture or compare register
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