UPD70F3765GF-GAT-AX Renesas Electronics America, UPD70F3765GF-GAT-AX Datasheet - Page 1128

• Manufacturer Part Number: UPD70F3765GF-GAT-AX
• Description: MCU 32BIT V850ES/JX3-H 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Hr

Specifications of UPD70F3765GF-GAT-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 48MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3-H, V850ES/JH3-H
21.6.4 Data hold registers
R01UH0042EJ0400 Rev.4.00
Sep 30, 2010
(1) UF0 EP0 read register (UF0E0R)
UF0E0R
The UF0E0R register is a 64-byte FIFO that stores the OUT data sent from the host in the data stage of control
transfer to/from Endpoint0.
This register is read-only, in 8-bit units. A write access to this register is ignored.
The hardware automatically transfers data to the UF0E0R register when it has received the data from the host.
When the data has been correctly received, the E0ODT bit of the UF0IS1 register is set to 1. The UF0E0L register
holds the quantity of the received data, and an interrupt request (INTUSBF0) is issued. The UF0E0L register
always updates the length of the received data while it is receiving data. If the final transfer is correct reception, the
interrupt request is generated. If the reception is abnormal, the UF0E0L register is cleared to 0 and the interrupt
request is not generated.
The data held by the UF0E0R register must be read by FW up to the value of the amount of data read by the
UF0E0L register. Check that all data has been read by using the EP0R bit of the UF0EPS0 register (EP0R bit = 0
when all data has been read). If the value of the UF0E0L register is 0, the EP0NKR bit of the UF0E0N register is
cleared to 0, and the UF0E0R register is ready for reception. The UF0E0R register is cleared when the next
SETUP token has been received.
Caution Read all the data stored. Clear the FIFO to discard some data.
The operation of the UF0E0R register is illustrated below.
Bit position
7 to 0
E0R7
7
E0R7 to E0R0
Bit name
E0R6
6
E0R5
These bits store the OUT data sent from the host in the data stage of control transfer
to/from Endpoint0.
5
E0R4
4
E0R3
CHAPTER 21 USB FUNCTION CONTROLLER (USBF)
3
E0R2
2
Function
E0R1
1
E0R0
0
00200100H
Address
Page 1128 of 1509
After reset
Undefined