UPD70F3765GF-GAT-AX Renesas Electronics America, UPD70F3765GF-GAT-AX Datasheet - Page 1091

• Manufacturer Part Number: UPD70F3765GF-GAT-AX
• Description: MCU 32BIT V850ES/JX3-H 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Hr

Specifications of UPD70F3765GF-GAT-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 48MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3-H, V850ES/JH3-H
R01UH0042EJ0400 Rev.4.00
Sep 30, 2010
(11) UF0 INT status 0 register (UF0IS0)
UF0IS0
Bit position
Caution In the USBF, multiple interrupt sources, such as Bus Reset, Resume, and Short, are ORed
This register indicates the interrupt source. If the contents of this register are changed, the EPCINT0B signal
becomes active.
This register is read-only, in 8-bit units.
If an interrupt request (INTUSBF0) is generated from USBF, the FW must read this register to identify the interrupt
source.
Each bit of this register is forcibly cleared to 0 when 0 is written to the corresponding bit of the UF0IC0 register.
7
6
4
BUSRST
7
internally and are issued as a single interrupt request (INTUSBF0). Therefore, in the case of the
occurrence of multiple interrupt sources, they are ORed and issued as an INTUSBF0 interrupt
request.
For example, if a Bus Reset interrupt source and Resume interrupt source occur, the two
sources are ORed and an INTUSBF0 interrupt request is issued.
Under these conditions, if the Bus Reset interrupt source is cleared to 0 (UF0IC0.BUSRSTC = 0),
the V850ES/JG3-H or V850ES/JH3-H internal INTUSBF0 interrupt request may remain set to 1
since the Resume interrupt source will still remain.
(US0BIC.US0BIF), therefore, might not be set to 1.
In this case, after performing clear processing for each interrupt request with the INTUSBF0
interrupt servicing routine, confirm the flag status for the UF0IS0 and UF0IS1 registers again,
and if there are any interrupt sources with flags set to 1, perform flag clearing (only the
applicable bits need to be cleared (do not perform a batch clearing)).
BUSRST
RSUSPD
SHORT
Bit name
RSUSPD
6
This bit indicates that Bus Reset has occurred.
This bit indicates that the Resume or Suspend status has occurred. Reference bit 7 of
the UF0EPS1 register by FW.
This bit indicates that data is read from the FIFO of either the UF0BO1 or UF0BO2
register and that the USBSPnB signal (n = 2, 4) is active. It is valid only when the FIFO is
full in the DMA mode.
Identify on which endpoint the operation is performed, by using the UF0DMS1 register.
This bit is not automatically cleared to 0 even when the UF0DMS1 register is read by FW.
5
0
1: Bus Reset has occurred (interrupt request is generated).
0: Not Bus Reset status (default value)
1: Resume or Suspend status has occurred (interrupt request is generated).
0: Resume or Suspend status has not occurred (default value).
1: USBSPnB signal is active (interrupt request is generated).
0: USBSPnB signal is not active (default value).
SHORT
4
DMAED
CHAPTER 21 USB FUNCTION CONTROLLER (USBF)
3
SETRQ
2
CLRRQ
Function
1
EPHALT
The new interrupt request flag
0
00200020H
Address
Page 1091 of 1509
After reset
00H
(1/2)