UPD70F3765GF-GAT-AX Renesas Electronics America, UPD70F3765GF-GAT-AX Datasheet - Page 423

• Manufacturer Part Number: UPD70F3765GF-GAT-AX
• Description: MCU 32BIT V850ES/JX3-H 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Hr

Specifications of UPD70F3765GF-GAT-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 48MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3-H, V850ES/JH3-H
8.5.7
the valid edge input to the TIABnm pin has been detected, the count value of the 16-bit counter is stored in the
TABnCCRm register, and the 16-bit counter is cleared to 0000H.
signal (INTTABnCCm) occurs.
pins by using the TABnIOC1 register.
clock is fixed to the TIAB00 pin. At this time, clear the TAB0IOC1.TAB0IS1 and TAB0IOC1.TAB0IS0 bits to 00 (capture
trigger input (TIAB00 pin): No edge detected).
to TIAB13 pins.
R01UH0042EJ0400 Rev.4.00
Sep 30, 2010
In the pulse width measurement mode, TABn starts counting when the TABnCTL0.TABnCE bit is set to 1. Each time
The interval of the valid edge can be measured by reading the TABnCCRm register after a capture interrupt request
Select one of the TIABn0 to TIABn3 pins as the capture trigger input pin. Specify “No edge detected” for the unused
When an external clock is used as the count clock, measure the pulse width of the TIAB0k pin because the external
For TAB1, the external clock is input from the EVTAB1 pin, and the pulse width can be measured by using the TIAB10
Remark
Pulse width measurement mode (TABnMD2 to TABnMD0 bits = 110)
(external event
count input
trigger input)
trigger input)
trigger input)
trigger input)
TIAB00 pin
TIABn1 pin
TIABn2 pin
TIABn3 pin
Note TAB1: EVTAB1 pin
Remark
m = 0 to 3,
n = 0, 1
k = 1 to 3
(capture
(capture
(capture
capture
Note
Internal count clock
/
n = 0, 1
Figure 8-34. Configuration in Pulse Width Measurement Mode
detector
detector
detector
detector
detector
Edge
Edge
Edge
Edge
Edge
selection
TABnCE
Count
clock
bit
CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB)
TABnCCR0
(capture)
register
TABnCCR1
(capture)
register
TABnCCR2
(capture)
register
16-bit counter
TABnCCR3
(capture)
register
Clear
INTTABnOV signal
INTTABnCC0 signal
INTTABnCC1 signal
INTTABnCC2 signal
INTTABnCC3 signal
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