UPD70F3765GF-GAT-AX Renesas Electronics America, UPD70F3765GF-GAT-AX Datasheet - Page 597

• Manufacturer Part Number: UPD70F3765GF-GAT-AX
• Description: MCU 32BIT V850ES/JX3-H 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Hr

Specifications of UPD70F3765GF-GAT-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 48MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3-H, V850ES/JH3-H
R01UH0042EJ0400 Rev.4.00
Sep 30, 2010
(2) PWM output of 0%/100%
<1> 0% output is selected by the valley interrupt (without a match with the 16-bit counter).
<2> 0% output is canceled by the crest interrupt (without a match with the 16-bit counter).
<3> 0% output is selected by the crest interrupt (with a match with the 16-bit counter).
<4> 0% output is canceled by the valley interrupt (without a match with the 16-bit counter).
Remarks 1.
The V850ES/V850ES/JG3-H and V850ES/JH3-H are capable of 0% wave output and 100% wave output for PWM
output.
A low level is continuously output from the TOAB1Tm pin as the 0% wave output. A high level is continuously
output from the TOAB1Tm pin as the 100% wave output.
A 0% wave is output by setting the TAB1CCRm register to “M + 1” when the TAB1CCR0 register = M.
A 100% wave is output by setting the TAB1CCRm register to “0000H”.
Rewriting the TAB1CCRm register is enabled while the timer is operating, and 0% wave output or 100% wave
output can be selected at the point of the crest interrupt (INTTAB1CC0) and valley interrupt (INTTAB1OV).
Remark
The valley interrupt forcibly lowers the timer output. This produces the 0% output.
The crest interrupt forcibly raises the timer output. This cancels the 0% output.
The crest interrupt forcibly raises the timer output, but lowering the timer output takes precedence when
the value of the TAB1CCRm register matches the value of the 16-bit counter. As a result, the 0% wave is
output.
The valley interrupt forcibly lowers the timer output. This cancels the 0% output.
of timer output
buffer register
Forced timing
TAB1CCR1
TAB1CCR0
2. m = 1 to 3
TOAB1T1
TOAB1B1
pin output
pin output
m = 1 to 3
register
register
counter
CCR1
16-bit
means forcible raising and means forcible lowering.
0000H
Figure 11-9. 0% PWM Output Waveform (With Dead Time)
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<1>
0% output
M + 1
M + 1
M
CHAPTER 11 MOTOR CONTROL FUNCTION
<2>
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<3>
M + 1
0% output
M + 1
<4>
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