UPD70F3765GF-GAT-AX Renesas Electronics America, UPD70F3765GF-GAT-AX Datasheet - Page 519

• Manufacturer Part Number: UPD70F3765GF-GAT-AX
• Description: MCU 32BIT V850ES/JX3-H 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Hr

Specifications of UPD70F3765GF-GAT-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 48MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3-H, V850ES/JH3-H
R01UH0042EJ0400 Rev.4.00
Sep 30, 2010
• Compare operation
When the TT0CE bit is set to 1, 16-bit timer/event counter T starts counting, and the output signal of the TOT0n pin is
inverted. When the count value of the 16-bit counter later matches the set value of the TT0CCRn register, a compare
match interrupt request signal (INTTT0CCn) is generated, and the output signal of the TOT0n pin is inverted.
The 16-bit counter continues counting in synchronization with the count clock. When it counts up to FFFFH, it
generates an overflow interrupt request signal (INTTT0OV) at the next clock, is cleared to 0000H, and continues
counting. At this time, the overflow flag (TT0OPT0.TT0OVF bit) is also set to 1. Confirm that the overflow flag is set
to 1 and then clear it to 0 by executing the CLR instruction via software.
The TT0CCRn register can be rewritten while the counter is operating. If it is rewritten, the new value is reflected at
that time by anytime write, and compared with the count value.
INTTT0CC0 signal
INTTT0CC1 signal
TT0CCR0 register
TT0CCR1 register
TOT00 pin output
TOT01 pin output
INTTT0OV signal
16-bit counter
TT0OVF bit
TT0CE bit
Figure 9-34. Basic Timing in Free-Running Timer Mode (Compare Function)
FFFFH
0000H
D
10
D
00
D
10
CLR instruction
Cleared to 0 by
D
00
D
CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT)
10
D
00
CLR instruction
Cleared to 0 by
D
11
D
01
CLR instruction
Cleared to 0 by
D
11
D
D
D
01
01
11
CLR instruction
Cleared to 0 by
D
11
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