UPD70F3765GF-GAT-AX Renesas Electronics America, UPD70F3765GF-GAT-AX Datasheet - Page 1402

• Manufacturer Part Number: UPD70F3765GF-GAT-AX
• Description: MCU 32BIT V850ES/JX3-H 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Hr

Specifications of UPD70F3765GF-GAT-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 48MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3-H, V850ES/JH3-H
R01UH0042EJ0400 Rev.4.00
Sep 30, 2010
(5) Securement of communication serial interface
• On-chip debug mode register (OCDM)
• Serial interface registers
• Interrupt mask register
UARTC0, CSIF0, or CSIF3 is used for communication between MINICUBE2 and the target system. The settings
related to the serial interface modes are performed by the debug monitor program, but if the setting is changed by
the user program, a communication error may occur.
To prevent such a problem from occurring, communication serial interface must be secured in the user program.
[How to secure communication serial interface]
Do not set the registers related to CSIF0, CSIF3, or UARTC0 in the user program.
When CSIF0 is used, do not mask the transfer end interrupt (INTCF0R). When CSIF3 is used, do not mask the
transfer end interrupt (INTCF3R). When UARTC0 is used, do not mask the reception completion interrupt
(INTUC0R).
For the on-chip debug function using the UARTC0, CSIF0, or CSIF3, set the OCDM register functions to normal
mode. Be sure to set as follows.
• Input low level to the P56/INTP05/DRST pin.
• Set the OCDM0 bit as shown below.
(a) When CSIF0 is used
(b) When CSIF3 is used
(C) When UARTC0 is used
Remark
<1> Clear the OCDM0 bit to 0.
<2> Fix the P56/INTP05/DRST pin input to low level until the processing of <1> is complete.
CF0RIC
CF3RIC
UC0RIC
×: don’t care
×
7
×
7
×
7
0
6
6
0
6
0
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5
×
5
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4
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4
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4
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3
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3
×
3
×
CHAPTER 32 ON-CHIP DEBUG FUNCTION
2
×
2
×
2
×
1
1
×
×
1
×
0
0
×
×
0
×
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