UPD70F3765GF-GAT-AX Renesas Electronics America, UPD70F3765GF-GAT-AX Datasheet - Page 376

• Manufacturer Part Number: UPD70F3765GF-GAT-AX
• Description: MCU 32BIT V850ES/JX3-H 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Hr

Specifications of UPD70F3765GF-GAT-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 48MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3-H, V850ES/JH3-H
R01UH0042EJ0400 Rev.4.00
Sep 30, 2010
<1> Count operation start flow
<2> TABnCCR0 to TABnCCR3 register
<3> TABnCCR0 register setting change flow
Setting of TABnCCR1 register
Setting of TABnCCR0, TABnCCR2,
Setting of TABnCCR0 register
Setting of TABnCCR1 register
TABnCCR0 to TABnCCR3
(TABnCKS0 to TABnCKS2
setting change flow
Register initial setting
Remark
TABnCTL1 register,
TABnIOC0 register,
TABnIOC2 register,
and TABnCCR3 registers
TABnCTL0 register
TABnCE bit = 1
registers
START
bits),
Figure 8-19. Software Processing Flow in External Trigger Pulse Output Mode (2/2)
m = 0 to 3,
n = 0, 1
The initial setting of these
registers is performed
before setting the
TABnCE bit to 1.
The TABnCKS0 to
TABnCKS2 bits can be
set at the same time
when counting is
enabled (TABnCE bit = 1).
Trigger wait status
Writing the TABnCCR1
register must be performed
after writing the TABnCCR0,
TABnCCR2, and TABnCCR3
registers.
When the counter is cleared
after setting, the value
of the TABnCCRm register is
transferred to the CCRm buffer
registers.
Writing the same value to
the TABnCCR1 register is
necessary only when the
set cycle is changed.
When the counter is
cleared after setting,
the value of the TABnCCRm
register is transferred to
the CCRm buffer register.
CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB)
<4> TABnCCR1 to TABnCCR3 register
<6> TABnCCR1 register setting change flow
<7> Count operation stop flow
<5> TABnCCR2, TABnCCR3 register
Setting of TABnCCR1 register
Setting of TABnCCR1 register
Setting of TABnCCR1 register
Setting of TABnCCR2,
Setting of TABnCCR2,
setting change flow
setting change flow
TABnCCR3 registers
TABnCCR3 registers
TABnCE bit = 0
STOP
Writing the TABnCCR1
register must be performed
only when the set duty factor is
changed after writing the
TABnCCR2 and TABnCCR3
registers.
When the counter is cleared
after setting, the value of the
TABnCCRm register is transferred
to the CCRm buffer register.
Writing the same value to the
TABnCCR1 register is necessary
only when the set duty factor of
the TOABn2 and TOABn3 pin
outputs is changed.
When the counter is cleared
after setting, the value of the
TABnCCRm register is
transferred to the CCRm buffer
register.
The TABnCCR1 register only needs
to be written, only when the set duty
factor of the TOABn1 pin output is
changed.
When the counter is cleared after
setting, the value of the TABnCCRm
register is transferred to the CCRm
buffer register.
Counting is stopped.
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