UPD70F3765GF-GAT-AX Renesas Electronics America, UPD70F3765GF-GAT-AX Datasheet - Page 1109

• Manufacturer Part Number: UPD70F3765GF-GAT-AX
• Description: MCU 32BIT V850ES/JX3-H 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Hr

Specifications of UPD70F3765GF-GAT-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 48MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3-H, V850ES/JH3-H
R01UH0042EJ0400 Rev.4.00
Sep 30, 2010
(26) UF0 INT & DMARQ register (UF0IDR)
Remark
UF0IDR
Bit position
Caution If the target endpoint is not supported by the SET_INTERFACE request under DMA transfer, the
This register selects reporting via an interrupt request or starting DMA.
This register can be read or written in 8-bit units.
If data exists in either the UF0BO1 or UF0BO1 register, or if data can be written to the UF0BI1 or UF0BI2 register,
this register selects whether it is reported to the FW by an interrupt request, or whether starting DMA is requested.
If starting DMA is requested, the DMA transfer mode can be selected according to the setting of bits 0 and 1.
The related bits are invalid if each endpoint is not supported by the setting of the UF0EnIM register (n = 1 to 4)
and the current setting of the interface.
Be sure to clear bits 3 and 2 to “0”. If they are set to 1, the operation is not guaranteed.
7, 6
5, 4
n = 1, 2
m = 1 and x = 2 where n = 1
m = 3 and x = 4 where n = 2
DQBI2
MS
7
DMA request signal becomes inactive immediately, and the corresponding bit is automatically
cleared to 0 by hardware.
DQBInMS
DQBOnMS
Bit name
DQBI1
MS
6
DQBO2
MS
These bits enable (mask) a write DMA transfer request (DMA request signal for Endpoint
m) to the UF0BIn register. When these bits are set to 1, the DMA request signal for
Endpoint m becomes active while writing data can be acknowledged. If the DMA end
signal for Endpoint m is input (if the DMA controller issues TC), these bits are
automatically cleared to 0 by hardware. To continue DMA transfer, re-set these bits to 1
by FW.
These bits enable (mask) a read DMA transfer request (DMA request signal for Endpoint
x) to the UF0BOn register. When these bits are set to 1, the DMA request signal for
Endpoint x becomes active if the data to be read is prepared in the UF0BOn register. If
the DMA end signal for Endpoint x is input (if the DMA controller issues TC), these bits are
automatically cleared to 0 by hardware. They are also cleared to 0 when the USBSPxB
signal is active. To continue DMA transfer, re-set these bits to 1 by FW.
5
1: Enables active DMA request signal for Endpoint m (masks BKInDT interrupt).
0: Disables active DMA request signal for Endpoint m (default value).
1: Enables active DMA request signal for Endpoint x (masks BKOnDT interrupt).
0: Disables active DMA request signal for Endpoint x (default value).
DQBO1
MS
4
CHAPTER 21 USB FUNCTION CONTROLLER (USBF)
3
0
2
0
Function
MODE1
1
MODE0
0
0020004CH
Address
Page 1109 of 1509
After reset
00H
(1/2)