MC9S12E64CFU Freescale Semiconductor, MC9S12E64CFU Datasheet - Page 102

• Manufacturer Part Number: MC9S12E64CFU
• Description: IC MCU 64K FLASH 25MHZ 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12E64CFU

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 60
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 2.75 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Data Bus Width: 16 bit
• Data Ram Size: 4 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 60
• Number Of Timers: 16 bit
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• On-chip Dac: 8 bit, 2 Channel
• For Use With: M68EVB912E128 - BOARD EVAL FOR MC9S12E128/64
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No RoHS Version Available

Chapter 2 128 Kbyte Flash Module (FTS128K1V1)
All bits read 0 and are not writable.
2.4
2.4.1
Write operations are used for the program, erase, and erase verify algorithms described in this section. The
program and erase algorithms are controlled by a state machine whose timebase FCLK is derived from the
oscillator clock via a programmable divider. The FCMD register as well as the associated FADDR and
FDATA registers operate as a buffer and a register (2-stage FIFO) so that a new command along with the
necessary data and address can be stored to the buffer while the previous command is still in progress. This
pipelined operation allows a time optimization when programming more than one word on a specific row,
as the high voltage generation can be kept active in between two programming commands. The pipelined
operation also allows a simplification of command launching. Buffer empty as well as command
completion are signalled by flags in the FSTAT register with corresponding interrupts generated, if
enabled.
The next sections describe:
2.4.1.1
Prior to issuing any Flash command after a reset, it is first necessary to write the FCLKDIV register to
divide the oscillator clock down to within the 150-kHz to 200-kHz range. Since the program and erase
timings are also a function of the bus clock, the FCLKDIV determination must take this information into
account.
If we define:
102
Module Base + 0x000F
Reset
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W
R
How to write the FCLKDIV register
Command write sequence used to program, erase or erase verify the Flash array
Valid Flash commands
Errors resulting from illegal Flash operations
FCLK as the clock of the Flash timing control block
Tbus as the period of the bus clock
INT(x) as taking the integer part of x (e.g., INT(4.323) = 4),
Functional Description
Flash Command Operations
Writing the FCLKDIV Register
0
0
7
= Unimplemented or Reserved
0
0
6
MC9S12E128 Data Sheet, Rev. 1.07
0
0
5
Figure 2-20. RESERVED6
0
0
4
0
0
3
0
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Freescale Semiconductor
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0
1
0
0
0