MC9S12E64CFU Freescale Semiconductor, MC9S12E64CFU Datasheet - Page 129

• Manufacturer Part Number: MC9S12E64CFU
• Description: IC MCU 64K FLASH 25MHZ 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12E64CFU

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 60
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 2.75 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Data Bus Width: 16 bit
• Data Ram Size: 4 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 60
• Number Of Timers: 16 bit
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• On-chip Dac: 8 bit, 2 Channel
• For Use With: M68EVB912E128 - BOARD EVAL FOR MC9S12E128/64
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No RoHS Version Available

Refer to the ATD block description chapter for information on the ATDDIEN0 and ATDDIEN1 registers.
During reset, port AD pins are configured as high-impedance analog inputs (digital input buffer is
disabled).
3.3.1.1
Read: Anytime. Write: Anytime.
If the data direction bit of the associated I/O pin (DDRADx) is set to 1 (output), a write to the
corresponding I/O Register bit sets the value to be driven to the Port AD pin. If the data direction bit of the
associated I/O pin (DDRADx) is set to 0 (input), a write to the corresponding I/O Register bit takes place
but has no effect on the Port AD pin.
If the associated data direction bit (DDRADx) is set to 1 (output), a read returns the value of the I/O register
bit.
If the associated data direction bit (DDRADx) is set to 0 (input) and the associated ATDDIEN0(1) bit is
set to 0 (digital input buffer is disabled), the associated I/O register bit (PTADx) reads “1”.
If the associated data direction bit (DDRADx) is set to 0 (input) and the associated ATDDIEN0(1) bit is
set to 1 (digital input buffer is enabled), a read returns the value of the pin.
Freescale Semiconductor
KWU:
Reset
KWU:
Reset
ATD:
ATD:
W
W
R
R
KWAD15
PTAD15
KWAD7
PTAD7
AN15
AN7
Port AD I/O Register (PTAD)
0
0
7
7
KWAD14
PTAD14
KWAD6
PTAD6
AN14
AN6
0
0
6
6
Figure 3-2. Port AD I/O Register (PTAD)
KWAD13
PTAD13
KWAD5
PTAD5
AN13
AN5
MC9S12E128 Data Sheet, Rev. 1.07
0
0
5
5
PTAD12
KWAD4
KWA12
PTAD4
AN12
AN4
0
0
4
4
KWAD11
PTAD11
KWAD3
PTAD3
AN11
AN3
3
0
3
0
Chapter 3 Port Integration Module (PIM9E128V1)
KWAD10
PTAD10
KWAD2
PTAD2
AN10
AN2
0
0
2
2
KWAD9
KWAD1
PTAD9
PTAD1
AN9
AN1
1
0
1
0
KWAD8
KWAD0
PTAD8
PTAD0
AN8
AN0
0
0
0
0
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