MC9S12E64CFU Freescale Semiconductor, MC9S12E64CFU Datasheet - Page 118

• Manufacturer Part Number: MC9S12E64CFU
• Description: IC MCU 64K FLASH 25MHZ 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12E64CFU

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 60
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 2.75 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Data Bus Width: 16 bit
• Data Ram Size: 4 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 60
• Number Of Timers: 16 bit
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• On-chip Dac: 8 bit, 2 Channel
• For Use With: M68EVB912E128 - BOARD EVAL FOR MC9S12E128/64
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No RoHS Version Available

Chapter 2 128 Kbyte Flash Module (FTS128K1V1)
2.4.4
On each reset, the Flash module executes a reset sequence to hold CPU activity while loading the following
registers from the Flash array memory according to
2.4.4.1
If a reset occurs while any Flash command is in progress, that command will be immediately aborted. The
state of the word being programmed or the sector/array being erased is not guaranteed.
2.4.5
The Flash module can generate an interrupt when all Flash commands have completed execution or the
Flash address, data, and command buffers are empty.
2.4.5.1
Figure 2-26
The Flash module uses the CBEIF and CCIF flags in combination with the enable bits CBIE and CCIE to
discriminate for the generation of interrupts.
For a detailed description of these register bits, refer to
(FCNFG)”
118
•
•
FPROT — Flash Protection Register (see
FSEC — Flash Security Register (see
Flash Address, Data, and Command
Buffers are empty
All Flash commands have completed
execution
and
Flash Reset Sequence
Interrupts
shows the logic used for generating interrupts.
Reset While Flash Command Active
Description of Interrupt Operation
Vector addresses and their relative interrupt priority are determined at the
MCU level.
Section 2.3.2.6, “Flash Status Register
Interrupt Source
CBEIE
CBEIF
CCIE
CCIF
Figure 2-26. Flash Interrupt Implementation
Table 2-17. Flash Interrupt Sources
MC9S12E128 Data Sheet, Rev. 1.07
Section
(FSTAT register)
(FSTAT register)
Interrupt Flag
NOTE
Section
CBEIF
CCIF
Table
2.3.2.2)
(FSTAT)”.
Section 2.3.2.4, “Flash Configuration Register
FLASH INTERRUPT REQUEST
2.3.2.5)
2-1:
Local Enable
CBEIE
CCIE
Global (CCR) Mask
Freescale Semiconductor
I Bit
I Bit