MC9S12E64CFU Freescale Semiconductor, MC9S12E64CFU Datasheet - Page 170

• Manufacturer Part Number: MC9S12E64CFU
• Description: IC MCU 64K FLASH 25MHZ 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12E64CFU

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 60
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 2.75 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Data Bus Width: 16 bit
• Data Ram Size: 4 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 60
• Number Of Timers: 16 bit
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• On-chip Dac: 8 bit, 2 Channel
• For Use With: M68EVB912E128 - BOARD EVAL FOR MC9S12E128/64
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No RoHS Version Available

Chapter 4 Clocks and Reset Generator (CRGV4)
4.3.2.1
The SYNR register controls the multiplication factor of the PLL. If the PLL is on, the count in the loop
divider (SYNR) register effectively multiplies up the PLL clock (PLLCLK) from the reference frequency
by 2 x (SYNR+1). PLLCLK will not be below the minimum VCO frequency (f
Read: anytime
Write: anytime except if PLLSEL = 1
170
Reset
ARMCOP
Register
Name
W
R
CRG Synthesizer Register (SYNR)
0
0
7
If PLL is selected (PLLSEL=1), Bus Clock = PLLCLK / 2
Bus Clock must not exceed the maximum operating system frequency.
Write to this register initializes the lock detector bit and the track detector
bit.
W
R
= Unimplemented or Reserved
Bit 7
Bit 7
0
0
0
6
Figure 4-3. CRG Register Summary (continued)
Figure 4-4. CRG Synthesizer Register (SYNR)
= Unimplemented or Reserved
Bit 6
6
0
PLLCLK
SYN5
MC9S12E128 Data Sheet, Rev. 1.07
0
5
Bit 5
=
5
0
2xOSCCLKx
SYNR
NOTE
NOTE
0
4
Bit 4
4
0
---------------------------------- -
REFDV
SYNR
SYN3
0
3
Bit 3
+
+
3
0
1
1
SYN2
0
2
Bit 2
2
0
SCM
).
Freescale Semiconductor
SYN1
Bit 1
0
1
1
0
Bit 0
Bit 0
SYN0
0
0
0