MC9S12E64CFU Freescale Semiconductor, MC9S12E64CFU Datasheet - Page 230

• Manufacturer Part Number: MC9S12E64CFU
• Description: IC MCU 64K FLASH 25MHZ 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12E64CFU

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 60
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 2.75 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Data Bus Width: 16 bit
• Data Ram Size: 4 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 60
• Number Of Timers: 16 bit
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• On-chip Dac: 8 bit, 2 Channel
• For Use With: M68EVB912E128 - BOARD EVAL FOR MC9S12E128/64
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No RoHS Version Available

Chapter 6 Analog-to-Digital Converter (ATD10B16CV2)
6.3.2.16.2
6.4
The ATD10B16C is structured in an analog and a digital sub-block.
6.4.1
The analog sub-block contains all analog electronics required to perform a single conversion. Separate
power supplies V
6.4.1.1
The sample and hold (S/H) machine accepts analog signals from the external world and stores them as
capacitor charge on a storage node.
The sample process uses a two stage approach. During the first stage, the sample amplifier is used to
quickly charge the storage node.The second stage connects the input directly to the storage node to
complete the sample for high accuracy.
When not sampling, the sample and hold machine disables its own clocks. The analog electronics continue
drawing their quiescent current. The power down (ADPU) bit must be set to disable both the digital clocks
and the analog power consumption.
The input analog signals are unipolar and must fall within the potential range of V
230
R (10-BIT)
R (10-BIT)
R (8-BIT)
R (8-BIT)
Reset
Reset
W
W
Figure 6-20. Right Justified, ATD Conversion Result Register x, High Byte (ATDDRxH)
Figure 6-21. Right Justified, ATD Conversion Result Register x, Low Byte (ATDDRxL)
Functional Description
Analog Sub-block
BIT 7 MSB
Sample and Hold Machine
Right Justified Result Data
BIT 7
0
0
0
0
7
7
DDA
and V
= Unimplemented or Reserved
= Unimplemented or Reserved
BIT 6
BIT 6
SSA
6
0
0
0
6
0
allow to isolate noise of other MCU circuitry from the analog sub-block.
MC9S12E128 Data Sheet, Rev. 1.07
BIT 5
BIT 5
0
0
0
0
5
5
BIT 4
BIT 4
4
0
0
0
4
0
BIT 3
BIT 3
0
0
0
0
3
3
BIT 2
BIT 2
2
0
0
0
2
0
SSA
BIT 9 MSB
Freescale Semiconductor
BIT 1
BIT 1
to VDDA.
0
0
0
1
1
BIT 8
BIT 0
BIT 0
0
0
0
0
0