MC9S12E64CFU Freescale Semiconductor, MC9S12E64CFU Datasheet - Page 138

• Manufacturer Part Number: MC9S12E64CFU
• Description: IC MCU 64K FLASH 25MHZ 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12E64CFU

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 60
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 2.75 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Data Bus Width: 16 bit
• Data Ram Size: 4 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 60
• Number Of Timers: 16 bit
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• On-chip Dac: 8 bit, 2 Channel
• For Use With: M68EVB912E128 - BOARD EVAL FOR MC9S12E128/64
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No RoHS Version Available

Chapter 3 Port Integration Module (PIM9E128V1)
Read: Anytime. Write: Never, writes to this register have no effect.
This register always reads back the status of the associated pins.
3.3.2.3
Read: Anytime. Write: Anytime.
This register configures port pins PM[7:3] and PM[1:0] as either input or output.
If the IIC is enabled, the IIC controls the SCL and SDA I/O direction, and the corresponding DDRM[7:6]
bits have no effect on their I/O direction. Refer to the IIC block description chapter for details.
If the SCI2 transmitter is enabled, the I/O direction of the transmit pin TXD2 is controlled by SCI2, and
the DDRM5 bit has no effect. If the SCI2 receiver is enabled, the I/O direction of the receive pin RXD2 is
controlled by SCI2, and the DDRM4 bit has no effect. Refer to the SCI block description chapter for
further details.
If the DAC1 or DAC0 channel is enabled, the associated pin DAO1 or DAO0 is forced to be output, and
the associated DDRM1 or DDRM0 bit has no effect.
The DDRM bits do not change to reflect the pin I/O direction when not being used as GPIO. The
DDRM[7:3]; DDRM[1:0] bits revert to controlling the I/O direction of the pins when the associated IIC,
SCI, or DAC1/0 function are disabled.
138
DDRM[7:3,
7:3, 1:0
Reset
Field
1:0]
W
R
DDRM7
Data Direction Port M
0 Associated pin is configured as input.
1 Associated pin is configured as output.
Port M Data Direction Register (DDRM)
0
7
= Reserved or Unimplemented
DDRM6
0
6
Figure 3-12. Port M Data Direction Register (DDRM)
Table 3-9. DDRM Field Descriptions
DDRM5
MC9S12E128 Data Sheet, Rev. 1.07
0
5
DDRM4
0
4
Description
DDRM3
0
3
0
0
2
DDRM1
Freescale Semiconductor
0
1
DDRM0
0
0