MC9S12E64CFU Freescale Semiconductor, MC9S12E64CFU Datasheet - Page 430

• Manufacturer Part Number: MC9S12E64CFU
• Description: IC MCU 64K FLASH 25MHZ 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12E64CFU

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 60
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 2.75 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Data Bus Width: 16 bit
• Data Ram Size: 4 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 60
• Number Of Timers: 16 bit
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• On-chip Dac: 8 bit, 2 Channel
• For Use With: M68EVB912E128 - BOARD EVAL FOR MC9S12E128/64
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No RoHS Version Available

Chapter 13 Timer Module (TIM16B4CV1)
13.3.2.13 Main Timer Interrupt Flag 2 (TFLG2)
TFLG2 indicates when interrupt conditions have occurred. To clear a bit in the flag register, write the bit
to one.
Read: Anytime
Write: Used in clearing mechanism (set bits cause corresponding bits to be cleared).
Any access to TCNT will clear TFLG2 register if the TFFCA bit in TSCR register is set.
13.3.2.14 Timer Input Capture/Output Compare Registers High and Low 4–7
Depending on the TIOS bit for the corresponding channel, these registers are used to latch the value of the
free-running counter when a defined transition is sensed by the corresponding input capture edge detector
or to trigger an output action for output compare.
Read: Anytime
430
Reset
Field
TOF
7
W
Reset
R
Reset
W
R
W
R
TOF
Timer Overflow Flag — Set when 16-bit free-running timer overflows from 0xFFFF to 0x0000. This bit is cleared
automatically by a write to the TFLG2 register with bit 7 set. (See also TCRE control bit explanation.)
(TCxH and TCxL)
0
7
Figure 13-20. Timer Input Capture/Output Compare Register x High (TCxH)
Bit 15
Figure 13-21. Timer Input Capture/Output Compare Register x Low (TCxL)
15
Bit 7
0
0
7
Unimplemented or Reserved
0
0
6
Bit 14
Figure 13-19. Main Timer Interrupt Flag 2 (TFLG2)
14
Bit 6
0
0
6
Table 13-16. TRLG2 Field Descriptions
MC9S12E128 Data Sheet, Rev. 1.07
0
0
5
Bit 13
11
Bit 5
0
0
5
Bit 12
0
0
4
12
Bit 4
0
0
4
Description
Bit 11
0
0
3
11
Bit 3
0
0
3
Bit 10
0
0
2
10
Bit 2
0
0
2
Freescale Semiconductor
Bit 9
0
0
1
Bit 1
0
9
0
1
Bit 8
0
0
Bit 0
0
0
0
0
0