MC9S12E64CFU Freescale Semiconductor, MC9S12E64CFU Datasheet - Page 198

• Manufacturer Part Number: MC9S12E64CFU
• Description: IC MCU 64K FLASH 25MHZ 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12E64CFU

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 60
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 2.75 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Data Bus Width: 16 bit
• Data Ram Size: 4 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 60
• Number Of Timers: 16 bit
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• On-chip Dac: 8 bit, 2 Channel
• For Use With: M68EVB912E128 - BOARD EVAL FOR MC9S12E128/64
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No RoHS Version Available

Chapter 4 Clocks and Reset Generator (CRGV4)
The internal reset of the MCU remains asserted while the reset generator completes the 192 SYSCLK long
reset sequence. The reset generator circuitry always makes sure the internal reset is deasserted
synchronously after completion of the 192 SYSCLK cycles. In case the RESET pin is externally driven
low for more than these 192 SYSCLK cycles (external reset), the internal reset remains asserted too.
4.5.1
The CRGV4 generates a clock monitor reset in case all of the following conditions are true:
The reset event asynchronously forces the configuration registers to their default settings (see
“Memory Map and Register
doesn’t change the state of the CME bit, because it has already been set). As a consequence, the CRG
immediately enters self-clock mode and starts its internal reset sequence. In parallel the clock quality
check starts. As soon as clock quality check indicates a valid oscillator clock the CRG switches to
OSCCLK and leaves self-clock mode. Because the clock quality checker is running in parallel to the reset
generator, the CRG may leave self-clock mode while completing the internal reset sequence. When the
reset sequence is finished the CRG checks the internally latched state of the clock monitor fail circuit. If a
clock monitor fail is indicated processing begins by fetching the clock monitor reset vector.
4.5.2
When COP is enabled, the CRG expects sequential write of 0x0055 and 0x00AA (in this order) to the
ARMCOP register during the selected time-out period. As soon as this is done, the COP time-out period
restarts. If the program fails to do this the CRG will generate a reset. Also, if any value other than 0x0055
or 0x00AA is written, the CRG immediately generates a reset. In case windowed COP operation is enabled
198
•
•
•
Clock monitor is enabled (CME=1)
Loss of clock is detected
Self-clock mode is disabled (SCME=0)
Clock Monitor Reset
Computer Operating Properly Watchdog (COP) Reset
SYSCLK
RESET
Definition”). In detail the CME and the SCME are reset to logical ‘1’ (which
possibly
SYSCLK
not
running
CRG drives RESET pin low
MC9S12E128 Data Sheet, Rev. 1.07
) (
Figure 4-25. RESET Timing
128+n cycles
with n being
min 3 / max 6
cycles depending
on internal
synchronization
delay
) (
)
(
RESET pin
released
64 cycles
)
(
possibly
RESET
driven low
externally
)
(
Freescale Semiconductor
Section 4.3,