MC9S12E64CFU Freescale Semiconductor, MC9S12E64CFU Datasheet - Page 444

• Manufacturer Part Number: MC9S12E64CFU
• Description: IC MCU 64K FLASH 25MHZ 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12E64CFU

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 60
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 2.75 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Data Bus Width: 16 bit
• Data Ram Size: 4 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 60
• Number Of Timers: 16 bit
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• On-chip Dac: 8 bit, 2 Channel
• For Use With: M68EVB912E128 - BOARD EVAL FOR MC9S12E128/64
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No RoHS Version Available

Chapter 14 Dual Output Voltage Regulator (VREG3V3V2)
The regulator is a linear series regulator with a bandgap reference in its full-performance mode and a
voltage clamp in reduced-power mode. All load currents flow from input V
reference circuits are connected to V
14.4.2
In full-performance mode, a fraction of the output voltage (V
fed to an operational amplifier. The amplified input voltage difference controls the gate of an output driver
which basically is a large NMOS transistor connected to the output.
14.4.3
In reduced-power mode, the driver gate is connected to a buffered fraction of the input voltage (V
The operational amplifier and the bandgap are disabled to reduce power consumption.
14.4.4
sub-block LVD is responsible for generating the low-voltage interrupt (LVI). LVD monitors the input
voltage (V
status flag LVDS changes its value. The LVD is available in FPM and is inactive in reduced-power mode
and shutdown mode.
14.4.5
This functional block monitors output V
V
Due to its role during chip power-up this module must be active in all operating modes of VREG3V3V2.
14.4.6
Block LVR monitors the primary output voltage V
LVR asserts and when rising above the deassertion level (V
function is available only in full-performance mode.
14.4.7
This part contains the register block of VREG3V3V2 and further digital functionality needed to control
the operating modes. CTRL also represents the interface to the digital core logic.
444
PORD
, the signal goes low. The transition to low forces the CPU in the power-on sequence.
DDA
Full-Performance Mode
Reduced-Power Mode
LVD — Low-Voltage Detect
POR — Power-On Reset
LVR — Low-Voltage Reset
CTRL — Regulator Control
–V
SSA
) and continuously updates the status flag LVDS. Interrupt flag LVIF is set whenever
DDA
MC9S12E128 Data Sheet, Rev. 1.07
DD
and V
. If V
SSA
DD
DD
.
is below V
. If it drops below the assertion level (V
LVRD
DD
PORD
) and the bandgap reference voltage are
) signal LVR negates again. The LVR
, signal POR is high, if it exceeds
DDR
to V
Freescale Semiconductor
SS
or V
LVRA
SSPLL
) signal
, the
DDR
).