MC9S12E64CFU Freescale Semiconductor, MC9S12E64CFU Datasheet - Page 408

• Manufacturer Part Number: MC9S12E64CFU
• Description: IC MCU 64K FLASH 25MHZ 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12E64CFU

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 60
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 2.75 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Data Bus Width: 16 bit
• Data Ram Size: 4 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 60
• Number Of Timers: 16 bit
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• On-chip Dac: 8 bit, 2 Channel
• For Use With: M68EVB912E128 - BOARD EVAL FOR MC9S12E128/64
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No RoHS Version Available

Chapter 12 Pulse-Width Modulator (PWM8B6CV1)
12.4.2.4
Each channel has a dedicated 8-bit up/down counter which runs at the rate of the selected clock source
(reference
a duty register and a period register as shown in
register the output flip-flop changes state causing the PWM waveform to also change state. A match
between the PWM counter and the period register behaves differently depending on what output mode is
selected as shown in
Section 12.4.2.6, “Center Aligned Outputs.”
Each channel counter can be read at anytime without affecting the count or the operation of the PWM
channel.
Any value written to the counter causes the counter to reset to 0x0000, the counter direction to be set to
up, the immediate load of both duty and period registers with values from the buffers, and the output to
change according to the polarity bit. When the channel is disabled (PWMEx = 0), the counter stops. When
a channel becomes enabled (PWMEx = 1), the associated PWM counter continues from the count in the
PWMCNTx register. This allows the waveform to resume when the channel is re-enabled. When the
channel is disabled, writing 0 to the period register will cause the counter to reset on the next selected
clock.
Generally, writes to the counter are done prior to enabling a channel to start from a known state. However,
writing a counter can also be done while the PWM channel is enabled (counting). The effect is similar to
writing the counter when the channel is disabled except that the new period is started immediately with
the output set according to the polarity bit.
The counter is cleared at the end of the effective period (see
Section 12.4.2.6, “Center Aligned Outputs,”
408
Figure 12-34
When PWMCNTx register
written to any value
Effective period ends
PWM Timer Counters
Counter Clears (0x0000)
If the user wants to start a new “clean” PWM waveform without any
“history” from the old waveform, the user must write to channel counter
(PWMCNTx) prior to enabling the PWM channel (PWMEx = 1).
Writing to the counter while the channel is enabled can cause an irregular
PWM cycle to occur.
Figure 12-35
for the available clock sources and rates). The counter compares to two registers,
Table 12-11. PWM Timer Counter Conditions
and described in
MC9S12E128 Data Sheet, Rev. 1.07
When PWM channel is
enabled (PWMEx = 1). Counts
from last value in PWMCNTx.
for more details).
Counter Counts
Figure
NOTE
NOTE
Section 12.4.2.5, “Left Aligned Outputs,”
12-35. When the PWM counter matches the duty
Section 12.4.2.5, “Left Aligned Outputs,”
When PWM channel is
disabled (PWMEx = 0)
Counter Stops
Freescale Semiconductor
and
and