MC9S12E64CFU Freescale Semiconductor, MC9S12E64CFU Datasheet - Page 506

• Manufacturer Part Number: MC9S12E64CFU
• Description: IC MCU 64K FLASH 25MHZ 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12E64CFU

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 60
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 2.75 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Data Bus Width: 16 bit
• Data Ram Size: 4 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 60
• Number Of Timers: 16 bit
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• On-chip Dac: 8 bit, 2 Channel
• For Use With: M68EVB912E128 - BOARD EVAL FOR MC9S12E128/64
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No RoHS Version Available

Chapter 17 Interrupt (INTV1)
The interrupt sub-block decodes the priority of all system exception requests and provides the applicable
vector for processing the exception. The INT supports I-bit maskable and X-bit maskable interrupts, a
non-maskable unimplemented opcode trap, a non-maskable software interrupt (SWI) or background debug
mode request, and three system reset vector requests. All interrupt related exception requests are managed
by the interrupt sub-block (INT).
17.1.1
The INT includes these features:
17.1.2
The functionality of the INT sub-block in various modes of operation is discussed in the subsections that
follow.
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Provides two to 122 I-bit maskable interrupt vectors (0xFF00–0xFFF2)
Provides one X-bit maskable interrupt vector (0xFFF4)
Provides a non-maskable software interrupt (SWI) or background debug mode request vector
(0xFFF6)
Provides a non-maskable unimplemented opcode trap (TRAP) vector (0xFFF8)
Provides three system reset vectors (0xFFFA–0xFFFE) (reset, CMR, and COP)
Determines the appropriate vector and drives it onto the address bus at the appropriate time
Signals the CPU that interrupts are pending
Provides control registers which allow testing of interrupts
Provides additional input signals which prevents requests for servicing I and X interrupts
Wakes the system from stop or wait mode when an appropriate interrupt occurs or whenever XIRQ
is active, even if XIRQ is masked
Provides asynchronous path for all I and X interrupts, (0xFF00–0xFFF4)
(Optional) selects and stores the highest priority I interrupt based on the value written into the
HPRIO register
Normal operation
The INT operates the same in all normal modes of operation.
Special operation
Interrupts may be tested in special modes through the use of the interrupt test registers.
Emulation modes
The INT operates the same in emulation modes as in normal modes.
Low power modes
See
Section 17.4.1, “Low-Power
Features
Modes of Operation
MC9S12E128 Data Sheet, Rev. 1.07
Modes,” for details
Freescale Semiconductor