MC9S12E64CFU Freescale Semiconductor, MC9S12E64CFU Datasheet - Page 387

• Manufacturer Part Number: MC9S12E64CFU
• Description: IC MCU 64K FLASH 25MHZ 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12E64CFU

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 60
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 2.75 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Data Bus Width: 16 bit
• Data Ram Size: 4 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 60
• Number Of Timers: 16 bit
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• On-chip Dac: 8 bit, 2 Channel
• For Use With: M68EVB912E128 - BOARD EVAL FOR MC9S12E128/64
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No RoHS Version Available

12.3.2.1
Each PWM channel has an enable bit (PWMEx) to start its waveform output. When any of the PWMEx
bits are set (PWMEx = 1), the associated PWM output is enabled immediately. However, the actual PWM
waveform is not available on the associated PWM output until its clock source begins its next cycle due to
the synchronization of PWMEx and the clock source.
An exception to this is when channels are concatenated. After concatenated mode is enabled (CONxx bits
set in PWMCTL register), enabling/disabling the corresponding 16-bit PWM channel is controlled by the
low-order PWMEx bit. In this case, the high-order bytes PWMEx bits have no effect and their
corresponding PWM output lines are disabled.
While in run mode, if all six PWM channels are disabled (PWME5–PWME0 = 0), the prescaler counter
shuts off for power savings.
Read: anytime
Write: anytime
Freescale Semiconductor
PWME5
PWME4
PWME3
PWME2
Reset
Field
5
4
3
2
W
R
Pulse Width Channel 5 Enable
0 Pulse width channel 5 is disabled.
1 Pulse width channel 5 is enabled. The pulse modulated signal becomes available at PWM,output bit 5 when
Pulse Width Channel 4 Enable
0 Pulse width channel 4 is disabled.
1 Pulse width channel 4 is enabled. The pulse modulated signal becomes available at PWM, output bit 4 when
Pulse Width Channel 3 Enable
0 Pulse width channel 3 is disabled.
1 Pulse width channel 3 is enabled. The pulse modulated signal becomes available at PWM, output bit 3 when
Pulse Width Channel 2 Enable
0 Pulse width channel 2 is disabled.
1 Pulse width channel 2 is enabled. The pulse modulated signal becomes available at PWM, output bit 2 when
PWM Enable Register (PWME)
0
0
7
its clock source begins its next cycle.
its clock source begins its next cycle. If CON45 = 1, then bit has no effect and PWM output line 4 is disabled.
its clock source begins its next cycle.
its clock source begins its next cycle. If CON23 = 1, then bit has no effect and PWM output line 2 is disabled.
The first PWM cycle after enabling the channel can be irregular.
= Unimplemented or Reserved
0
0
6
Figure 12-3. PWM Enable Register (PWME)
Table 12-2. PWME Field Descriptions
PWME5
MC9S12E128 Data Sheet, Rev. 1.07
0
5
PWME4
NOTE
0
4
Description
PWME3
0
3
Chapter 12 Pulse-Width Modulator (PWM8B6CV1)
PWME2
0
2
PWME1
0
1
PWME0
0
0
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