71M6531F-IM/F Maxim Integrated Products, 71M6531F-IM/F Datasheet - Page 11

• Manufacturer Part Number: 71M6531F-IM/F
• Description: IC ENERGY METER 256KB 68-QFN
• Manufacturer: Maxim Integrated Products

Specifications of 71M6531F-IM/F

• Mounting Style: SMD/SMT
• Package / Case: QFN-68
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

(IBP/IBN), and VB of the device. Additionally, using the alternate multiplexer selection, it has the ability to
select temperature and the battery voltage. The multiplexer can be operated in two modes:
•
•
The alternate multiplexer cycles are usually performed infrequently (every second or so) by the MPU. In
order to prevent disruption of the voltage tracking PLL and voltage allpass networks, VA is not replaced in
the ALT selections.
engine (CE) fills in missing samples due to an ALT multiplexer sequence.
possible multiplexer state sequences.
In a typical application, IA (IAN/IAP) and IB (IBN/IBP) are connected to current transformers that sense
the current on each phase of the line voltage. VA and VB are typically connected to voltage sensors
through resistor dividers.
The multiplexer control circuit (MUX_CTRL signal) controls multiplexer advance, FIR initiation and VREF
chopping. Additionally, MUX_CTRL launches each pass through the CE program. Conceptually,
MUX_CTRL is clocked by CK32, the 32768 Hz clock from the PLL block. The behavior of MUX_CTRL is
governed by MUX_ALT, EQU[2:0], CHOP_E[1:0] and MUX_DIV[3:0].
The MUX_ALT bit requests an alternative multiplexer frame. The bit may be asserted on any MPU cycle
and may be subsequently de-asserted on any cycle including the next one. A rising edge on MUX_ALT
will cause MUX_CTRL to wait until the next multiplexer frame and implement a single alternate multiplexer
frame.
Another control input to the MUX is MUX_DIV[3:0]. These four bits can request from 1 to 10 multiplexer
states per frame. The multiplexer always starts at the beginning of its list and proceeds until the number
of states defined by MUX_DIV[3:0] have been converted.
FDS 6531/6532 005
1.2.2
The input multiplexer supports up to four input signals that are applied to pins IA (IAP/IAN), VA, IB
The sequence of sampled channels is fully programmable using I/O RAM registers. SLOTn_SEL[3:0]
selects the input for the nth state in a standard multiplexer frame, while SLOTn_ALTSEL[3:0] selects the
input for the nth state in an alternate multiplexer frame. The states shown in
v1.3
Time
Slot
During a normal multiplexer cycle, the signals from the IA (IAP/IAN), IB (IBP/IBN), VA and VB pins
are selected.
During the alternate multiplexer cycle, the temperature signal (TEMP) and the battery monitor are
selected, along with some of the voltage and/or current signal sources shown in Table
unnecessary drainage on the battery, the battery monitor is only active when enabled with the BME
bit (0x2020[6]) in the I/O RAM.
0
1
2
3
–
–
–
–
–
–
Input Multiplexer
SLOT0_SEL[3:0]
SLOT1_SEL[3:0]
SLOT2_SEL[3:0]
SLOT3_SEL[3:0]
SLOT4_SEL[3:0]
SLOT5_SEL[3:0]
SLOT6_SEL[3:0]
SLOT7_SEL[3:0]
SLOT8_SEL[3:0]
SLOT9_SEL[3:0]
Table 1: Inputs Selected in Regular and Alternate Multiplexer Cycles
Register
Table 1
© 2005-2010 TERIDIAN Semiconductor Corporation
Regular Slot
details the regular and alternative multiplexer sequences. The computation
Address
Typical Selections
RAM
0
1
2
3
–
–
–
–
–
–
Signal for
ADC
VB
VA
IA
IB
–
–
–
–
–
–
SLOT0_ALTSEL[3:0]
SLOT1_ALTSEL[3:0]
SLOT2_ALTSEL[3:0]
SLOT3_ALTSEL[3:0]
SLOT4_ALTSEL[3:0]
SLOT5_ALTSEL[3:0]
SLOT6_ALTSEL[3:0]
SLOT7_ALTSEL[3:0]
SLOT8_ALTSEL[3:0]
SLOT9_ALTSEL[3:0]
Register
Data Sheet 71M6531D/F-71M6532D/F
Alternate Slot
Table 1
Address
Typical Selections
RAM
A
B
–
–
1
3
–
–
–
–
are examples for
1.
To prevent
Signal for
TEMP
VBAT
ADC
VB
VA
–
–
–
–
–
–
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