71M6531F-IM/F Maxim Integrated Products, 71M6531F-IM/F Datasheet - Page 25

• Manufacturer Part Number: 71M6531F-IM/F
• Description: IC ENERGY METER 256KB 68-QFN
• Manufacturer: Maxim Integrated Products

Specifications of 71M6531F-IM/F

• Mounting Style: SMD/SMT
• Package / Case: QFN-68
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

FDS 6531/6532 005
v1.3
ERASE
(FLSH_ERASE)
FL_BANK
PGADDR
(FLSH_PGADR[5:0])
FLSHCRL
IFLAGS
INTBITS
(INT0 … INT6)
(Alternate Name)
Register
0xB6[2:0]
0xF8[6:0]
Address
0xB2[0]
0xB2[1]
0xB2[6]
0xB2[7]
0xE8[0]
0xE8[1]
0xE8[2]
0xE8[3]
0xE8[4]
0xE8[5]
0xE8[6]
0xE8[7]
0xF8[7]
© 2005-2010 TERIDIAN Semiconductor Corporation
0xB7
0x94
SFR
Only byte operations on the entire INTBITS register should be used when
writing. The byte must have all bits set except the bits that are to be
cleared.
IE_XFER
INT6 … INT0
FLSH_PWE
FLSH_MEEN
SECURE
PREBOOT
IE_RTC
FWCOL1
FWCOL0
IE_PB
IE_WAKE
PLL_RISE
PLL_FALL
WD_RST
Bit Field
Name
R/W
R/W Flash Bank Selection.
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
W
W
W
R
R
This register is used to initiate either the Flash
Mass Erase cycle or the Flash Page Erase cycle.
See the
Flash Page Erase Address register. Contains
the flash memory page address (page 0 through
page 127) that will be erased during the Page
Erase cycle (default = 0x00).
Must be re-written for each new Page Erase
cycle.
Program Write Enable:
Mass Erase Enable:
Must be re-written for each new Mass Erase
cycle.
Enables security provisions that prevent external
reading of flash memory and CE program RAM.
This bit is reset on chip reset and may only be
set. Attempts to write zero are ignored.
Indicates that the preboot sequence is active.
This flag monitors the XFER_BUSY interrupt.
It is set by hardware and must be cleared by
the interrupt handler.
This flag monitors the RTC_1SEC interrupt. It
is set by the hardware and must be cleared by
the interrupt handler.
This flag indicates that a flash write was in
progress while the CE was busy.
This flag indicates that a flash write was
attempted when the CE was attempting to
begin a code pass.
This flag indicates that the wake-up pushbutton
was pressed.
This flag indicates that the MPU was awakened
by the autowake timer.
PLL_RISE Interrupt Flag:
Write 0 to clear the PLL_RISE interrupt flag.
PLL_FALL Interrupt Flag:
Write 0 to clear the PLL_FALL interrupt flag.
Interrupt inputs. The MPU may read these bits
to see the status of external interrupts INT0 up
to INT6. These bits do not have any memory
and are primarily intended for debug use.
The WDT is reset when a 1 is written to this
bit.
0: MOVX commands refer to XRAM
1: MOVX @DPTR,A moves A to Program
0: Mass Erase disabled (default).
1: Mass Erase enabled.
Space (Flash) @ DPTR.
Space, normal operation (default).
Flash Memory
Data Sheet 71M6531D/F-71M6532D/F
Description
section for details.
25