71M6531F-IM/F Maxim Integrated Products, 71M6531F-IM/F Datasheet - Page 27

• Manufacturer Part Number: 71M6531F-IM/F
• Description: IC ENERGY METER 256KB 68-QFN
• Manufacturer: Maxim Integrated Products

Specifications of 71M6531F-IM/F

• Mounting Style: SMD/SMT
• Package / Case: QFN-68
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

SM20 (S0CON[5]) for UART0, or SM21 (S1CON[5] for UART1, set to 1. When the master processor outputs
the slave’s address, it sets the 9
processors compare the received byte with their address. If there is a match, the addressed slave will
clear SM20 or SM21 and receive the rest of the message. All other slaves will ignore the message. After
addressing the slave, the host outputs the rest of the message with the 9
FDS 6531/6532 005
The feature of receiving 9 bits (Mode 3 for UART0, Mode A for UART1) can be used as handshake signals
for inter-processor communication in multi-processor systems. In this case, the slave processors have bit
serial port receive interrupts will be generated.
UART Control Registers:
The functions of UART0 and UART1 depend on the setting of the Serial Port Control Registers S0CON
and S1CON shown in
v1.3
S0CON[7]
S0CON[6]
S0CON[5]
S0CON[4]
S0CON[3]
S0CON[2]
S0CON[1]
S0CON[0]
S1CON[7]
S1CON[5]
S1CON[4]
S1CON[3]
Bit
Bit
Since the TI0, RI0, TI1 and RI1 bits are in an SFR bit addressable byte, common practice
would be to clear them with a bit operation, but this must be avoided
bit operations as a byte wide read-modify-write hardware macro. If an interrupt occurs after
the read, but before the write, its flag will be cleared unintentionally.
The proper way to clear these flag bits is to write a byte mask consisting of all ones except for
a zero in the location of the bit to be cleared. The flag bits are configured in hardware to ignore
ones written to them.
SM0
SM1
SM20
REN0
TB80
RB80
TI0
RI0
SM
SM21
REN1
TB81
Symbol
Symbol
Table 17
© 2005-2010 TERIDIAN Semiconductor Corporation
Table 17: The S0CON (UART0) Register (SFR 0x98)
Table 18: The S1CON (UART1) register (SFR 0x9B)
and
The SM0 and SM1 bits set the UART0 mode:
Enables the inter-processor communication feature.
If set, enables serial reception. Cleared by software to disable reception.
The 9th transmitted data bit in Modes 2 and 3. Set or cleared by the
MPU, depending on the function it performs (parity check, multiprocessor
communication etc.)
In Modes 2 and 3 it is the 9
RB80 is the stop bit. In mode 0, this bit is not used. Must be cleared by
software.
Transmit interrupt flag; set by hardware after completion of a serial transfer.
Must be cleared by software.
Receive interrupt flag; set by hardware after completion of a serial reception.
Must be cleared by software.
Sets the baud rate and mode for UART1.
Enables the inter-processor communication feature.
If set, enables serial reception. Cleared by software to disable reception.
The 9
depending on the function it performs (parity check, multiprocessor
communication etc.)
th
bit to 1, causing a serial port receive interrupt in all the slaves. The slave
Table 18,
SM
th
Mode
0
1
transmitted data bit in Mode A. Set or cleared by the MPU,
0
1
2
3
respectively and the PCON register shown in
Mode
A
B
N/A
8-bit UART
9-bit UART
9-bit UART
Description
9-bit UART
8-bit UART
Description
th
data bit received. In Mode 1, SM20 is 0,
Function
Function
Data Sheet 71M6531D/F-71M6532D/F
SM0
0
0
1
1
th
variable
variable
bit set to 0, so no additional
Baud Rate
. The hardware implements
SM1
0
1
0
1
Table
19.
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