71M6531F-IM/F Maxim Integrated Products, 71M6531F-IM/F Datasheet - Page 52

• Manufacturer Part Number: 71M6531F-IM/F
• Description: IC ENERGY METER 256KB 68-QFN
• Manufacturer: Maxim Integrated Products

Specifications of 71M6531F-IM/F

• Mounting Style: SMD/SMT
• Package / Case: QFN-68
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

(e.g. the current PC value, loop counters, flags, etc.) before a WDT reset occurs.
Data Sheet 71M6531D/F-71M6532D/F
1.5.16 Hardware Watchdog Timer
V3P3 - 10mV
Figure 17: Functions defined by V1
The WDT can be disabled by tying the V1 pin to V3P3 (see
V1 power fault detection. Since there is no method in firmware to disable the crystal oscillator or the
WDT, it is guaranteed that whatever state the part might find itself in, upon watchdog overflow, the part
will be reset to a known state.
Asserting ICE_E will also deactivate the WDT. This is the only method that will work in BROWNOUT
mode. In normal operation, the WDT is reset by periodically writing a one to the WDT_RST bit. The
watchdog timer is also reset when the internal signal WAKE = 0 (see Section
If enabled with the IEN_WD_NROVF bit in I/O RAM, an interrupt occurs roughly 1 ms before the WDT resets
the chip. This can be used to determine the cause of a WDT reset since it allows the code to log its state
52
400mV
V3P3 -
VBIAS
V3P3
0V
V1
operation,
enabled
Normal
Battery
WDT dis-
modes
WDT
abled
© 2005-2010 TERIDIAN Semiconductor Corporation
An independent, robust, fixed-duration, watchdog timer (WDT) is included
in the 71M6531D/F and 71M6532D/F. It uses the RTC crystal oscillator as
its time base and must be refreshed by the MPU firmware at least every
1.5 seconds. When not refreshed on time, the WDT overflows and the part
is reset as if the RESET pin were pulled high, except that the I/O RAM bits
will be in the same state as after a wake-up from SLEEP or LCD modes
(see the I/O RAM description in Section
after RESET and wake-up). 4100 oscillator cycles (or 125 ms) after the
WDT overflow, the MPU will be launched from program address 0x0000.
A status bit, WD_OVF, is set when the WDT overflow occurs. This bit is
powered by the nonvolatile supply and can be read by the MPU when
WAKE rises to determine if the part is initializing after a WDT overflow
event or after a power-up. After it is read, the MPU firmware must clear
WD_OVF. The WD_OVF bit is also cleared by the RESET pin.
There is no internal digital state that deactivates the WDT.
Figure
17). Of course, this also deactivates
4.2
for a list of I/O RAM bit states
2.5 Wake-Up
FDS 6531/6532 005
Behavior).
v1.3