71M6531F-IM/F Maxim Integrated Products, 71M6531F-IM/F Datasheet - Page 72

• Manufacturer Part Number: 71M6531F-IM/F
• Description: IC ENERGY METER 256KB 68-QFN
• Manufacturer: Maxim Integrated Products

Specifications of 71M6531F-IM/F

• Mounting Style: SMD/SMT
• Package / Case: QFN-68
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Data Sheet 71M6531D/F-71M6532D/F
4
4.1
In Table 54, unimplemented (U) and reserved (R) bits are shaded in light gray. Unimplemented bits have no memory storage, writing them has no
effect, and reading them always returns zero. Reserved bits may be in use and should not be changed from the values given in parentheses.
Writing values other than those shown in parenthesis to reserved bits may have undesirable side effects and must be avoided.
Non-volatile bits are shaded in dark gray. Non-volatile bits are backed-up during power failures if the system includes a battery connected to the
VBAT pin.
This table lists only the SFR registers that are not generic 8051 SFR registers. Bits marked with † apply to the 71M6531D/F only, bits marked with
‡ apply to the 71M6532D/F only and should be 0 for the other device.
72
CE0
CE1
CE2
COMP0
CONFIG0
CONFIG1
VERSION
CONFIG2
CE3
CE4
CE5
WAKE
TMUX
ANACTRL
CONFIG3
CONFIG4
INTBITS
IFLAGS
ERASE
FLSHCTL
FL_BANK
PGADR
Configuration:
Interrupts and WD Timer:
Flash Memory:
Name
Firmware Interface
I/O RAM and SFR Map – Functional Order
SFR F8
SFR E8
SFR 94
SFR B2
SFR B6
SFR B7
20AA
20AB
20AC
20AD
Addr
209D
20A7
20A8
20A9
2000
2001
2002
2003
2004
2005
2006
2007
IE_PLLFALL
WAKE_ARM
VREF_CAL
PREBOOT
WD_RST
Bit 7
PRE_SAMPS[1:0]
U
U
OPT_TXE[1:0]
U
U
U
IE_PLLRISE
EQU[2:0]
PLS_INV
SECURE
PLL_OK
SLEEP
Bit 6
INT6
U
U
© 2005-2010 TERIDIAN Semiconductor Corporation
R (0000)
Table 54: I/O RAM Map in Functional Order
U
WRPROT_BT
LCD_ONLY
SEL_IBN‡
IE_WAKE
ECK_DIS
EX_PLL
Bit 5
R (0)
INT5
FLSH_PGADR[5:0]
U
U
U
CHOP_E[1:0]
WRPROT_CE
EX_FWCOL
CHOP_IB‡
CKOUT_E
M26MHZ
IE_PB
CE_E
Bit 4
R (0)
INT4
FLSH_ERASE[7:0]
U
U
BOOT_SIZE[7:0]
CE_LCTN[7:0]
VERSION[7:0]
IE_FWCOL1
WAKE_RES
CE10MHZ
VREF_DIS
RTM_E
ADC_E
Bit 3
INT3
SUM_CYCLES[5:0]
U
FIR_LEN[1:0]
U
U
U
LCD_DAC[2:0]
IE_FWCOL0
TMUX[4:0]
MUX_ALT
WD_OVF
Bit 2
INT2
U
MUX_DIV[3:0]
WAKE_PRD[2:0]
MPU_DIV[2:0]
FLBANK[2:0]
FLSH_MEEN
SEL_IAN‡
EX_RTC
IE_RTC
R (0)
Bit 1
INT1
U
U
U
OPT_FDC[1:0]
FDS 6531/6532 005
U
CHOP_I_EN‡
COMP_STAT
FLSH_PWE
CHOP_IA‡
M40MHZ
IE_XFER
EX_XFR
Bit 0
R (0)
INT0
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