71M6531F-IM/F Maxim Integrated Products, 71M6531F-IM/F Datasheet - Page 60

• Manufacturer Part Number: 71M6531F-IM/F
• Description: IC ENERGY METER 256KB 68-QFN
• Manufacturer: Maxim Integrated Products

Specifications of 71M6531F-IM/F

• Mounting Style: SMD/SMT
• Package / Case: QFN-68
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

power fault block, is greater than VBIAS, the internal 2.5 V regulator will continue to provide power to the
digital section.
Once initiated, the reset mode will persist until the reset timer times out, signified by WAKE rising. This
will occur in 4100 cycles of the real time clock after RESET goes low, at which time the MPU will begin
executing it’s pre-boot and boot sequences from address 00. See the
Flash Memory
If system power is not present, the reset timer duration will be 2 cycles of the crystal clock at which time
the MPU will begin executing in BROWNOUT mode, starting at address 00.
When the output of the comparator falls (V1<VBIAS), the I/O RAM bits PLL_OK are zeroed and the part
switches to BROWNOUT mode if a battery is present. Once system power returns, the MPU remains in
reset and does not transition to MISSION mode until 2048 to 4096 CK32 clock cycles later, when PLL_OK
rises. If a battery is not present, as indicated by BAT_OK=0, WAKE will fall and the part will enter SLEEP
mode.
There are several conditions the device could be in as system power returns. If the part is in BROWNOUT
mode, it will automatically switch to MISSION mode when PLL_OK rises. It will receive an interrupt indicating
this. No configuration bits will be reset or reconfigured during this transition.
If the part is in LCD or SLEEP mode when system power returns, it will also switch to MISSION mode
when PLL_OK rises. In this case, all configuration bits will be in the reset state due to WAKE having
been zero. The RTC clock will not be disturbed, but the MPU RAM must be re-initialized. The hardware
watchdog timer will become active when the part enters MISSION mode.
If there is no battery when system power returns, the part will switch to MISSION mode when PLL_OK
rises. All configuration bits will be in reset state and RTC and MPU RAM data will be unknown and must
be initialized by the MPU.
Data Sheet 71M6531D/F-71M6532D/F
2.4
2.4.1
When the RESET pin is pulled high, all digital activity stops. The oscillator and RTC module continue to
run. Additionally, all I/O RAM bits are set to their default states. As long as V1, the input voltage at the
2.4.2
The 71M6531D/F and 71M6532D/F include a comparator to monitor system power fault conditions.
60
Fault and Reset Behavior
Reset Mode
Power Fault Circuit
section for additional descriptions of pre-boot and boot.
MPU Clock
MPU Mode
VBAT_OK
RESETZ
PLL_OK
Current
Internal
Battery
Source
WAKE
VBAT
© 2005-2010 TERIDIAN Semiconductor Corporation
Figure 24: Power-Up Timing with VBAT only
1024 CK32
cycles
14.5 CK32
Xtal
cycles
BROWNOUT
Program Security
time
FDS 6531/6532 005
description in the
v1.3