71M6531F-IM/F Maxim Integrated Products, 71M6531F-IM/F Datasheet - Page 44

• Manufacturer Part Number: 71M6531F-IM/F
• Description: IC ENERGY METER 256KB 68-QFN
• Manufacturer: Maxim Integrated Products

Specifications of 71M6531F-IM/F

• Mounting Style: SMD/SMT
• Package / Case: QFN-68
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

registers for data access. The direction control of these pins is achieved with the LCD_SEGn[3] bits and
data access is controlled with the LCD_SEGn[0] bits in I/O RAM.
DIO56 through DIO58 are dedicated DIO pins. They are controlled with DIO_DIR56[7] through
DIO_DIR58[7] and with DIO_56[4] through DIO_58[4] in I/O RAM.
or the LCD_SEGn registers. Input and output data are written to or read from the pins using SFR registers
P0, P1, and P2.
DIO24 and higher do not have SFR registers for direction control. DIO40 and higher do not have SFR
registers for data access. The direction control of these pins is achieved with the LCD_SEGn[3] registers
and data access is controlled with the LCD_SEGn[0] registers in I/O RAM.
Data Sheet 71M6531D/F-71M6532D/F
DIO24 and higher do not have SFR registers for direction control. DIO40 and higher do not have SFR
1.5.9
On reset or power-up, all DIO pins are inputs until they are configured for the desired direction under
MPU control. The pin function can be configured by the I/O RAM bits LCD_BITMAPn. Setting
LCD_BITMAPn = 1 configures the pin for LCD, setting LCD_BITMAPn = 0 configures it for DIO. Once a
pin is configured as DIO, it can be configured independently as an input or output with the DIO_DIR bits
44
DIO Pin n Function
Since the control for DIO24 through DIO51 is shared with the control for LCD segments, the firmware
must take care not to disturb the DIO pins when accessing the LCD segments and vice versa. Usually,
this requires reading the I/O RAM register, applying a mask and writing back the modified byte.
Table 44: Data/Direction Registers and Internal Resources for DIO 40-51 (71M6532D/F)
Digital IO – Common Characteristics for 71M6531D/F and 71M6532D/F
Configuration (DIO
or LCD segment)
Data Register
Direction Register
0 = input,
1 = output
Table 45: DIO_DIR Control Bit
LCD Segment
Pin number
DIO
© 2005-2010 TERIDIAN Semiconductor Corporation
Input
LCD_BITMAP[63:56]
40
60
95
DIO_DIR [n]
4
0
41
61
97
5
Output
42
62
98
6
1
43
63
40
7
44
64
31
0
Table 46: Selectable Control using DIO_DIR Bits
DIO_R
Value
45
65
38
1
0
1
2
3
4
5
6
7
–
–
–
–
LCD_BITMAP[71:64]
–
–
Resource Selected for DIO Pin
None
Reserved
T0 (counter 0 clock)
T1 (counter 1 clock)
High priority I/O interrupt (INT0 rising)
Low priority I/O interrupt (INT1 rising)
High priority I/O interrupt (INT0 falling)
Low priority I/O interrupt (INT1 falling)
47
67
22
3
48
68
23
4
49
69
24
5
FDS 6531/6532 005
50
70
25
6
51
71
50
7
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