71M6531F-IM/F Maxim Integrated Products, 71M6531F-IM/F Datasheet - Page 30

• Manufacturer Part Number: 71M6531F-IM/F
• Description: IC ENERGY METER 256KB 68-QFN
• Manufacturer: Maxim Integrated Products

Specifications of 71M6531F-IM/F

• Mounting Style: SMD/SMT
• Package / Case: QFN-68
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

corresponding flag can be individually enabled or disabled by the enable bits in SFRs IEN0 (SFR 0xA8),
IEN1 (SFR 0xB8), and IEN2 (SFR 0x9A).
Referring to
Internal Sources) or can originate from other parts of the 71M653x SoC (referred to as External Sources).
There are seven external interrupt sources, as seen in the leftmost part of
Table 25
the interrupt service has begun, it can be interrupted only by a higher priority interrupt. The interrupt service
is terminated by a return from instruction, RETI. When an RETI is performed, the processor will return to
the instruction that would have been next when the interrupt occurred.
When the interrupt condition occurs, the processor will also indicate this by setting a flag bit. This bit is
set regardless of whether the interrupt is enabled or disabled. Each interrupt flag is sampled once per
machine cycle, after that, samples are polled by the hardware. If the sample indicates a pending interrupt
when the interrupt is enabled, then the interrupt request flag is set. On the next instruction cycle, the interrupt
will be acknowledged by hardware forcing an LCALL to the appropriate vector address, if the following
conditions are met:
•
•
•
Special Function Registers for Interrupts
The following SFR registers control the interrupt functions:
•
•
•
•
Data Sheet 71M6531D/F-71M6532D/F
1.4.8
There is no internal software watchdog timer. Use the standard watchdog timer instead (see
Hardware Watchdog
1.4.9
The 80515 MPU provides 11 interrupt sources with four priority levels. Each source has its own request
flag(s) located in a special function register (TCON, IRCON and SCON). Each interrupt requested by the
Interrupt Overview
When an interrupt occurs, the MPU will vector to the predetermined address as shown in
30
No interrupt of equal or higher priority is already in progress.
An instruction is currently being executed and is not completed.
The instruction in progress is not RETI or any write access to the registers IEN0, IEN1, IEN2, IP0 or IP1.
The interrupt enable registers: IEN0, IEN1 and IEN2 (see
The Timer/Counter control registers, TCON and T2CON (see
The interrupt request register, IRCON (see
The interrupt priority registers: IP0 and IP1 (see
IEN0[7]
IEN0[6]
IEN0[5]
IEN0[4]
IEN0[3]
IEN0[2]
IEN0[1]
IEN0[0]
Bit
WD Timer (Software Watchdog Timer)
Interrupts
(i.e., EX0-EX6).
Figure
Symbol
WDT
EAL
ET1
EX1
ET0
EX0
ES0
–
8, interrupt sources can originate from within the 80515 MPU core (referred to as
Timer).
© 2005-2010 TERIDIAN Semiconductor Corporation
EAL = 0 disables all interrupts.
Not used for interrupt control.
Not Used.
ES0 = 0 disables serial channel 0 interrupt.
ET1 = 0 disables timer 1 overflow interrupt.
EX1 = 0 disables external interrupt 1.
ET0 = 0 disables timer 0 overflow interrupt.
EX0 = 0 disables external interrupt 0.
Table 24: The IEN0 Bit Functions (SFR 0xA8)
Figure 8
Table
shows the device interrupt structure.
Table
29).
34).
Function
Table
Table 27
24,
Table 25
and
Figure 8
Table
and
, and in
28).
Table
FDS 6531/6532 005
Table
Table 24
26.
1.5.16
36. Once
and
v1.3