71M6531F-IM/F Maxim Integrated Products, 71M6531F-IM/F Datasheet - Page 58

• Manufacturer Part Number: 71M6531F-IM/F
• Description: IC ENERGY METER 256KB 68-QFN
• Manufacturer: Maxim Integrated Products

Specifications of 71M6531F-IM/F

• Mounting Style: SMD/SMT
• Package / Case: QFN-68
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

this mode, the MPU clock has substantial short-term jitter.
The value of MPU_DIV[2:0] will be remembered (not changed) as the part enters and exits BROWNOUT.
MPU_DIV[2:0] will be ignored during BROWNOUT.
While PLL_OK = 0, the I/O RAM bits ADC_E and CE_E are held in the zero state disabling both the ADC and
the CE. When PLL_OK falls, the CE program counter is cleared immediately and all FIR processing halts.
each connected to pins SEG18 and SEG19, can be made to blink without the involvement of the MPU,
which is disabled in LCD mode. To minimize power, only segments that might be used should be
enabled.
LCD mode can be exited only by system power up, a timeout of the wake-up timer, or a push button.
When the IC exits LCD mode, the MPU can discover the event that caused the exit by reading the interrupt
flags and interpret them as follows:
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•
•
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After the transition from LCD mode to MISSION or BROWNOUT mode, the PC will be at 0x0000, the
XRAM is in an undefined state and the I/O RAM is only partially preserved (see the description of I/O RAM
states in Section 4.2). The GP0[7:0] through GP7[7:0] registers are preserved unless RESET goes high.
When the IC exits SLEEP mode, the MPU can discover the event that caused the exit by reading the
interrupt flags and interpret them as follows:
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•
•
•
After the transition from SLEEP mode to MISSION or BROWNOUT mode the PC will be at 0x0000, the
XRAM is in an undefined state and the I/O RAM is only partially preserved (see the description of I/O RAM
states in Section 4.2). The GP0[7:0] through GP7[7:0] registers are preserved unless RESET goes high.
Data Sheet 71M6531D/F-71M6532D/F
can voluntarily enter LCD or SLEEP modes. When system power is restored, the part will automatically
transition from any of the battery modes to MISSION mode, once the PLL has settled.
The MPU will run at 7/8 of the crystal clock rate. This permits the UARTs to be operated at 300 bd. In
2.3.2
In LCD mode, the data contained in the LCD_SEGn[3:0] fields is displayed. Up to four LCD segments,
2.3.3
In SLEEP mode, the battery current is minimized and only the Oscillator and RTC functions are active.
This mode can be exited only by system power-up, a timeout of the wake-up timer, or a push button event.
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IE_WAKE = 1 indicates that the wake timer has expired.
IE_PB =1 indicates that the pushbutton input (PB) was activated.
COMPSTAT = 0 indicates that a reset occurred but that main power is not yet available.
If none of the above conditions applies, system power (V3P3SYS) must have been restored
IE_WAKE = 1 indicates that the wake timer has expired.
IE_PB =1 indicates that the pushbutton input (PB) was activated.
COMPSTAT = 0 indicates that a reset occurred but that main power is not yet available.
If none of the above conditions applies, system power (V3P3SYS) must have been restored
LCD Mode
SLEEP Mode
© 2005-2010 TERIDIAN Semiconductor Corporation
FDS 6531/6532 005
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