71M6531F-IM/F Maxim Integrated Products, 71M6531F-IM/F Datasheet - Page 55

• Manufacturer Part Number: 71M6531F-IM/F
• Description: IC ENERGY METER 256KB 68-QFN
• Manufacturer: Maxim Integrated Products

Specifications of 71M6531F-IM/F

• Mounting Style: SMD/SMT
• Package / Case: QFN-68
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

the two serial output streams. In this example, MUX_DIV[3:0] = 4 and FIR_LEN[1:0] = 2 (384 CE cycles,
3 CK32 cycles per conversion), resulting in 13 CK32 cycles per multiplexer frame. Generally, the duration
of each MUX frame is:
•
•
•
CK32 cycle where the bandgap voltage is allowed to recover from the change in CROSS.
Each CE program pass begins when the ADC0 conversion (for IA) begins. Depending on the length of
the CE program, it may continue running until the end of the last conversion (ADC3). CE opcodes are
constructed to ensure that all CE code passes consume exactly the same number of cycles. The result of
each ADC conversion is inserted into the RAM when the conversion is complete. The CE code is written
to tolerate sudden changes in ADC data. The exact clock count when each ADC value is loaded into
FDS 6531/6532 005
2.2
Figure 19
An ADC conversion will always consume an integer number of CK32 clocks. Following this is a single
RAM is shown in
Figure 20
consisting of 140 CK cycles, will always finish before the next code pass starts.
v1.3
ADC TIMING
CE TIMING
TMUXOUT/RTM
ADC EXECUTION
CE_EXECUTION
RTM DATA 0 (32 bits)
RTM DATA 1 (32 bits)
RTM DATA 2 (32 bits)
RTM DATA 3 (32 bits)
1 + MUX_DIV * 1, if FIR_LEN[1:0] = 0 (138 CE cycles)
1 + MUX_DIV * 2, if FIR_LEN[1:0] = 1 (288 CE cycles)
1 + MUX_DIV * 3, if FIR_LEN[1:0] = 2 (384 CE cycles).
NOTES:
XFER_BUSY
MUX STATE
MUX_SYNC
MUX_SYNC
CE_BUSY
System Timing Summary
CKTEST
CK32
summarizes the timing relationships between the input MUX states, the CE_BUSY signal and
shows that the serial data stream, RTM, begins transmitting at the beginning of state S. RTM,
1. ALL DIMENSIONS ARE 5MHZ CK COUNTS.
2. THE PRECISE FREQUENCY OF CK IS 150*CRYSTAL FREQUENCY = 4.9152MHz.
3. XFER_BUSY OCCURS ONCE EVERY (PRE_SAMPS * SUM_CYCLES) CODE PASSES.
CK32
S
Figure 19: Timing Relationship between ADC MUX, Compute Engine
0
Figure 19.
FLAG
© 2005-2010 TERIDIAN Semiconductor Corporation
150
0
0
1
CK COUNT = CE_CYCLES + floor((CE_CYCLES + 2) / 5)
30 31
ADC0
Figure 20: RTM Output Format
450
INITIATED BY A CE OPCODE AT END OF SUMMATION INTERVAL
FLAG
1
0
MUX_DIV=4 (4 conversions) is shown
1
30
ADC MUX Frame
ADC1
31
900
FLAG
2
Data Sheet 71M6531D/F-71M6532D/F
0
1
ADC2
30
1350
31
FLAG
MAX CK COUNT
3
0
ADC3
1
30 31
1800
Settle
S
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