AT91SAM7X128 Atmel, AT91SAM7X128 Datasheet - Page 129

• Manufacturer Part Number: AT91SAM7X128
• Description: MCU 32-Bit 91S ARM7TDMI RISC 128KB Flash 1.8V/3.3V 100-Pin LQFP
• Manufacturer: Atmel

Specifications of AT91SAM7X128

• Package: 100LQFP
• Device Core: ARM7TDMI
• Family Name: 91S
• Maximum Speed: 55 MHz
• Ram Size: 32 KB
• Program Memory Size: 128 KB
• Operating Supply Voltage: 1.8|3.3 V
• Data Bus Width: 32 Bit
• Program Memory Type: Flash
• Number Of Programmable I/os: 62
• Interface Type: CAN/Ethernet/SPI/I2S/TWI/USART/USB
• On-chip Adc: 8-chx10-bit
• Operating Temperature: -40 to 85 °C
• Number Of Timers: 3

Table 20-18. Signal Description List (Continued)
20.3.2
20.3.3
6120H–ATARM–17-Feb-09
Signal Name
TST
PGMEN0
PGMEN1
TCK
TDI
TDO
TMS
Entering Serial Programming Mode
Read/Write Handshake
Function
Test Mode Select
Test Mode Select
Test Mode Select
JTAG TCK
JTAG Test Data In
JTAG Test Data Out
JTAG Test Mode Select
The following algorithm puts the device in Serial Programming Mode:
Note:
Table 20-19. Reset TAP Controller and Go to Select-DR-Scan
The read/write handshake is done by carrying out read/write operations on two registers of the
device that are accessible through the JTAG:
• Apply GND, VDDIO, VDDCORE, VDDFLASH and VDDPLL.
• Apply XIN clock within T
• Wait for T
• Reset the TAP controller clocking 5 TCK pulses with TMS set.
• Shift 0x2 into the IR register (IR is 4 bits long, LSB first) without going through the Run-Test-
• Shift 0x2 into the DR register (DR is 4 bits long, LSB first) without going through the Run-
• Shift 0xC into the IR register (IR is 4 bits long, LSB first) without going through the Run-Test-
Idle state.
Test-Idle state.
Idle state.
After reset, the device is clocked by the internal RC oscillator. Before clearing RDY signal, if an
external clock ( > 32 kHz) is connected to XIN, then the device will switch on the external clock.
Else, XIN input is not considered. An higher frequency on XIN speeds up the programmer
handshake.
TDI
POR_RESET
Xt
X
X
X
X
X
X
.
AT91SAM7X512/256/128 Preliminary
POR_RESET
JTAG
Test
TMS
1
1
1
1
1
0
1
+ 32(T
Output
Type
Input
Input
Input
Input
Input
Input
TAP Controller State
Test-Logic Reset
Run-Test/Idle
Select-DR-Scan
SCLK
) if an external clock is available.
Active
Level
High
High
High
-
-
-
-
Comments
Must be connected to VDDIO.
Must be connected to VDDIO
Must be connected to VDDIO
Pulled-up input at reset
Pulled-up input at reset
Pulled-up input at reset
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