AT91SAM7X128 Atmel, AT91SAM7X128 Datasheet - Page 42

• Manufacturer Part Number: AT91SAM7X128
• Description: MCU 32-Bit 91S ARM7TDMI RISC 128KB Flash 1.8V/3.3V 100-Pin LQFP
• Manufacturer: Atmel

Specifications of AT91SAM7X128

• Package: 100LQFP
• Device Core: ARM7TDMI
• Family Name: 91S
• Maximum Speed: 55 MHz
• Ram Size: 32 KB
• Program Memory Size: 128 KB
• Operating Supply Voltage: 1.8|3.3 V
• Data Bus Width: 32 Bit
• Program Memory Type: Flash
• Number Of Programmable I/os: 62
• Interface Type: CAN/Ethernet/SPI/I2S/TWI/USART/USB
• On-chip Adc: 8-chx10-bit
• Operating Temperature: -40 to 85 °C
• Number Of Timers: 3

11.2.4.2
11.2.4.3
11.2.5
42
AT91SAM7X512/256/128 Preliminary
ARM Instruction Set Overview
Status Registers
Exception Types
A seventh processing mode, System Mode, does not have any banked registers. It uses the
User Mode registers. System Mode runs tasks that require a privileged processor mode and
allows them to invoke all classes of exceptions.
All other processor states are held in status registers. The current operating processor status is
in the Current Program Status Register (CPSR). The CPSR holds:
All five exception modes also have a Saved Program Status Register (SPSR) that holds the
CPSR of the task immediately preceding the exception.
The ARM7TDMI
The types of exceptions are:
Exceptions are generated by internal and external sources.
More than one exception can occur in the same time.
When an exception occurs, the banked version of R14 and the SPSR for the exception mode
are used to save state.
To return after handling the exception, the SPSR is moved to the CPSR, and R14 is moved to
the PC. This can be done in two ways:
The ARM instruction set is divided into:
ARM instructions can be executed conditionally. Every instruction contains a 4-bit condition
code field (bit[31:28]).
Table 11-2
• four ALU flags (Negative, Zero, Carry, and Overflow)
• two interrupt disable bits (one for each type of interrupt)
• one bit to indicate ARM or Thumb execution
• five bits to encode the current processor mode
• fast interrupt (FIQ)
• normal interrupt (IRQ)
• memory aborts (used to implement memory protection or virtual memory)
• attempted execution of an undefined instruction
• software interrupts (SWIs)
• by using a data-processing instruction with the S-bit set, and the PC as the destination
• by using the Load Multiple with Restore CPSR instruction (LDM)
• Branch instructions
• Data processing instructions
• Status register transfer instructions
• Load and Store instructions
• Coprocessor instructions
• Exception-generating instructions
gives the ARM instruction mnemonic list.
supports five types of exception and a privileged processing mode for each type.
6120H–ATARM–17-Feb-09