AT91SAM7X128 Atmel, AT91SAM7X128 Datasheet - Page 166

• Manufacturer Part Number: AT91SAM7X128
• Description: MCU 32-Bit 91S ARM7TDMI RISC 128KB Flash 1.8V/3.3V 100-Pin LQFP
• Manufacturer: Atmel

Specifications of AT91SAM7X128

• Package: 100LQFP
• Device Core: ARM7TDMI
• Family Name: 91S
• Maximum Speed: 55 MHz
• Ram Size: 32 KB
• Program Memory Size: 128 KB
• Operating Supply Voltage: 1.8|3.3 V
• Data Bus Width: 32 Bit
• Program Memory Type: Flash
• Number Of Programmable I/os: 62
• Interface Type: CAN/Ethernet/SPI/I2S/TWI/USART/USB
• On-chip Adc: 8-chx10-bit
• Operating Temperature: -40 to 85 °C
• Number Of Timers: 3

23.8
23.8.1
23.8.2
Table 23-2.
Notes:
166
Offset
0x10C
0x11C
0x12C
0x13C
0x100
0x104
0x108
0x110
0x114
0x118
0x120
0x124
0x128
0x130
0x134
0x138
0x140
0x144
0x148
0x7C
0xFC
0000
0x04
0x80
0x84
---
---
Advanced Interrupt Controller (AIC) User Interface
1. The reset value of this register depends on the level of the external interrupt source. All other sources are cleared at reset,
2. PID2...PID31 bit fields refer to the identifiers as defined in the Peripheral Identifiers Section of the product datasheet.
AT91SAM7X512/256/128 Preliminary
Base Address
Register Mapping
thus not pending.
Register Mapping
Register
Source Mode Register 0
Source Mode Register 1
---
Source Mode Register 31
Source Vector Register 0
Source Vector Register 1
---
Source Vector Register 31
Interrupt Vector Register
FIQ Interrupt Vector Register
Interrupt Status Register
Interrupt Pending Register
Interrupt Mask Register
Core Interrupt Status Register
Reserved
Reserved
Interrupt Enable Command Register
Interrupt Disable Command Register
Interrupt Clear Command Register
Interrupt Set Command Register
End of Interrupt Command Register
Spurious Interrupt Vector Register
Debug Control Register
Reserved
Fast Forcing Enable Register
Fast Forcing Disable Register
Fast Forcing Status Register
The AIC is mapped at the address 0xFFFF F000. It has a total 4-Kbyte addressing space. This
permits the vectoring feature, as the PC-relative load/store instructions of the ARM processor
support only an ± 4-Kbyte offset.
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
AIC_SMR31
AIC_SVR31
AIC_EOICR
AIC_SMR0
AIC_SMR1
AIC_SVR0
AIC_SVR1
AIC_FFER
AIC_FFDR
AIC_FFSR
AIC_CISR
AIC_IECR
AIC_IDCR
AIC_ICCR
AIC_ISCR
AIC_DCR
AIC_FVR
AIC_SPU
AIC_IMR
AIC_IVR
AIC_ISR
AIC_IPR
Name
---
---
---
---
---
Read-write
Read-write
Read-write
Read-write
Read-write
Read-write
Read-write
Read-write
Read-only
Read-only
Read-only
Read-only
Read-only
Read-only
Write-only
Write-only
Write-only
Write-only
Write-only
Write-only
Write-only
Read-only
Access
---
---
---
---
---
6120H–ATARM–17-Feb-09
Reset
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
---
---
---
---
---
---
---
---
---
---
---
---
(1)