AT91SAM7X128 Atmel, AT91SAM7X128 Datasheet - Page 642

• Manufacturer Part Number: AT91SAM7X128
• Description: MCU 32-Bit 91S ARM7TDMI RISC 128KB Flash 1.8V/3.3V 100-Pin LQFP
• Manufacturer: Atmel

Specifications of AT91SAM7X128

• Package: 100LQFP
• Device Core: ARM7TDMI
• Family Name: 91S
• Maximum Speed: 55 MHz
• Ram Size: 32 KB
• Program Memory Size: 128 KB
• Operating Supply Voltage: 1.8|3.3 V
• Data Bus Width: 32 Bit
• Program Memory Type: Flash
• Number Of Programmable I/os: 62
• Interface Type: CAN/Ethernet/SPI/I2S/TWI/USART/USB
• On-chip Adc: 8-chx10-bit
• Operating Temperature: -40 to 85 °C
• Number Of Timers: 3

41.2
41.2.1
41.2.1.1
41.2.1.2
41.2.1.3
41.2.1.4
41.2.1.5
41.2.1.6
642
AT91SAM7X256/128 Errata - Rev. A Parts
AT91SAM7X512/256/128 Preliminary
Analog-to-Digital Converter (ADC)
ADC: DRDY Bit Cleared
ADC: DRDY not Cleared on Disable
ADC: DRDY Possibly Skipped due to CDR Read
ADC: Possible Skip on DRDY when Disabling a Channel
ADC: GOVRE Bit is not Updated
ADC: GOVRE Bit is not Set when Reading CDR
Refer to
The DRDY Flag should be clear only after a read of ADC_LCDR (Last Converted Data Regis-
ter). A read of any ADC_CDRx register (Channel Data Register) automatically clears the DRDY
flag.
None
When reading LCDR at the same instant as an end of conversion, with DRDY already active,
DRDY is kept active regardless of the enable status of the current channel. This sets DRDY,
whereas new data is not stored.
None
Reading CDR for channel "y" at the same instant as an end of conversion on channel "x" with
EOC[x] already active, leads to skipping to set the DRDY flag if channel "x" is enabled.
Use of DRDY functionality with access to CDR registers should be avoided.
DRDY does not rise when disabling channel "y" at the same time as an end of "x" channel con-
version, although data is stored into CDRx and LCDR.
None.
Read of the Status Register at the same instant as an end of conversion leads to skipping the
update of the GOVRE (general overrun) flag. GOVRE is neither reset nor set.
For example, if reading the status while an end of conversion is occurring and:
None
When reading CDRy (Channel Data Register y) at the same instant as an end of conversion on
channel "x" with the following conditions:
1. GOVRE is active but DRDY is inactive, does not correspond to a new general overrun
2. GOVRE is inactive but DRDY is active, does correspond to a new general overrun con-
• EOC[x] already active,
Problem Fix/Workaround:
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
condition but the GOVRE flag is not reset.
dition but the GOVRE flag is not set.
Section 41.1 “Marking” on page
641.
6120H–ATARM–17-Feb-09