AT91SAM7X128 Atmel, AT91SAM7X128 Datasheet - Page 653

• Manufacturer Part Number: AT91SAM7X128
• Description: MCU 32-Bit 91S ARM7TDMI RISC 128KB Flash 1.8V/3.3V 100-Pin LQFP
• Manufacturer: Atmel

Specifications of AT91SAM7X128

• Package: 100LQFP
• Device Core: ARM7TDMI
• Family Name: 91S
• Maximum Speed: 55 MHz
• Ram Size: 32 KB
• Program Memory Size: 128 KB
• Operating Supply Voltage: 1.8|3.3 V
• Data Bus Width: 32 Bit
• Program Memory Type: Flash
• Number Of Programmable I/os: 62
• Interface Type: CAN/Ethernet/SPI/I2S/TWI/USART/USB
• On-chip Adc: 8-chx10-bit
• Operating Temperature: -40 to 85 °C
• Number Of Timers: 3

41.3.5
41.3.5.1
41.3.5.2
41.3.5.3
41.3.6
41.3.6.1
41.3.6.2
6120H–ATARM–17-Feb-09
Peripheral Input/Output (PIO)
Pulse Width Modulation Controller (PWM)
PIO: Leakage on PB27 - PB30
PIO: Electrical Characteristics on NRST, PA0-PA30 and PB0-PB26
PIO: Drive Low NRST, PA0-PA30 and PB0-PB26
PWM: Update when PWM_CCNTx = 0 or 1
PWM: Update when PWM_CPRDx = 0
When PB27, PB28, PB29 or PB30 (the I/O lines multiplexed with the analog inputs) are set as
digital inputs with pull-up disabled, the leakage can be 25 µA in worst case and 90 nA in typical
case per I/O when the I/O is set externally at low level.
Set the I/O to VDDIO by internal or external pull-up.
When NRST or PA0 - PA30 or PB0 - PB26 are set as digital inputs with pull-up enabled, the volt-
age of the I/O stabilizes at VPull-up.
Vpull-up
This condition causes a leakage through VDDIO. This leakage is 45 µA per pad in worst case at
3.3 V.
I Leakage
It is recommended to use an external pull-up if needed.
When NRST or PA0 - PA30 or PB0 - PB26 are set as digital inputs with pull-up enabled, driving
the I/O with an output impedance higher than 500 ohms may not drive the I/O to a logical zero.
Output impedance must be lower than 500 ohms.
If the Channel Counter Register value is 0 or 1, the Channel Period Register or Channel Duty
Cycle Register is directly modified when writing the Channel Update Register.
Check the Channel Counter Register before writing the update register.
When Channel Period Register equals 0, the period update is not operational.
Do not write 0 in the period register.
VPull-up Min
VDDIO - 0.65 V
Parameter
I Leakage at 3,3V
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
VPull-up Max
VDDIO - 0.45 V
Typ
2.5
AT91SAM7X512/256/128 Preliminary
µA
Max
45
µA
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